Select and configure from 36 rules in 6 categories
Signal Integrity, Power Integrity, EMC
EMC Adviser EX
Are you looking for a tool that enables you to meet the EMC requirements for your products? Then EMC Adviser EX is exactly the right solution for you! Using EMC Adviser speeds up the identification of EMC issues in an early design phase with reduced effort compared to manual checks.
Cross-probe and highlight within the design
Create summary reports and share as MS-Excel documents
With EMC Adviser for CR-8000, the circuit engineer is able to categorize EMC-relevant signals early-on in the schematic phase. The appropriate EMC rules are selected for the application and applied during the design phase, such as a DRC check.
EMC Adviser’s guidelines provide design issue recommendations, enabling non-expert users to solve Signal Integrity, Power Integrity, and EMC issues. Users can choose and configure from 36 rules in 6 categories, generate check results, cross-select, and highlight within the PCB layout, and create summary reports.
Summary reports with images and progress status can be shared as MS-Excel documents between the members of the development team. There is no need for any additional software to verify the identified EMC issues.
Rule categories and checks
- Are there any closed loops in my design?
- Are there any unintended open critical loops?
- Does any long track act as antenna?
- Are there any isolated copper shapes?
- Are any high-speed signals routed close to the edges of reference planes?
- Are there enough Vias spent along copper shapes to avoid effective antennas?
- Is there a potential to create current loops within copper shapes?
- How is the coverage of shielded signals?
- Is there any vertical shielding in Z-axis?
- Is any shielding missing in 4 directions (left/right/above/below)?
- Is the shield continued across Vias?
- How is the shielding coverage of defined net groups?
- How is the ground coverage beneath a component?
- Is the return path too far away from my high-speed signal?
- Are there any areas with high Via density? Identify cutouts and gaps caused by overlapping anti-pads.
- Is there a unique reference signal assigned to the high-speed signal?
- Is the lowest inductance path used for return currents between the boards? (Multi-board)
- Is there any impedance mismatch in critical signals?
- Is it necessary to add a specific termination to the high-speed signal?
- Find all 90-degree corners in my design
- Check all signals for critical line length
- How is the routing quality of differential signals?
- How large is the track capacitance? Is the maximum capacitive load exceeded?
- Check for crosstalk between active and passive signals
- Check for crosstalk between active signals and power nets
- How effective are the used EMC components?
- Is a signal marked for ground prohibition close to a ground net (same layer or adjacent layer)?
- How strong is the noise coupling between multiple boards? (Multiboard)
- Are Decaps too far away from the IC power pin?
- Are there any overlapping power planes that acts as noise bridges?
- Are any connectors affected by high-speed signals running over gaps?
- Are there any high-speed signals routed near a Via of a power net connected to a connector?
- Check the track width and number of Vias between the pin pairs
- How good is connection path length of used ESD components?
In this presentation, an EMC minded PCB design approach is presented, allowing designers to understand which EMC rules will apply to PCB projects and how EMC analysis capabilities can be utilized in the CAD flow to reduce the risk of EMC compliance failure once the board is manufactured.
In our webinar we will provide an introduction to the challenges of signal integrity and the underlying physical effects. This will provide the basis for practical tips to address the related challenges during PCB design.
DDR5 is the latest generation of memory. In this joint webinar with Keysight Technologies, we’ll begin with pre-layout simulation, then transition to CR-8000. The design will then be verified by Electromagnetic (EM) simulation and system simulations in Keysight ADS, in order to build confidence in the final DDR5 design.
EMC Adviser EX can be launched from these products
CR-8000 Design Force is the fastest, most effective PCB layout solution available today. Design Force enables design teams to layout and verify their designs in the context of a complete system or product.
Design Force offers an intuitive, integrated environment for designing single and multi-die packages for wire-bond, flip-chip, and high density advanced packaging.
Recent EMC Adviser EX Blog Posts
EMC problems are often responsible for re-design cycles in PCB design practice. Due to ever shorter innovation cycles of for example cell phones or IoT applications, such as fitness trackers or smartwatches, and many other electronic products, these time-consuming re-design cycles should be avoided under all circumstances.
In part 1 of this blog we took a back-to-basics approach and discussed line impedance and its effects in signal integrity. As every electrical conductor comprises capacitance, an inductance, and a frequency-dependent ohmic resistance, and with increasing frequencies, these electrical characteristics will influence and distort the signal.
Impedance and impedance control belong to the oldest and most often discussed topics in PCB design. They are especially important with the high-speed design when related to signal integrity. In this, the first of a two-part blog, we’ll go back to the basics of impedance/impedance control and consider what influences line impedance. In part two, we’ll set about controlling it.