signal integrity and emc issues

Signal Integrity, Power Integrity, EMC

Advanced Design Rule Checks

EMC Adviser EX: Analysis Tools and Design Rule Checks

Are you looking for a tool that enables you to meet the EMC requirements for your products? Then EMC Adviser EX is exactly the right solution for you! Using EMC Adviser speeds up the identification of EMC issues in an early design phase with reduced effort compared to manual checks.

Select and configure from 36 rules in 6 categories

Cross-probe and highlight within the design

Create summary reports and share as MS-Excel documents

Enhancing PCB Circuit Design: EMC Signal Categorization & Guided Solutions

With EMC Adviser for CR-8000, the circuit engineer is able to categorize EMC-relevant signals early-on in the schematic phase. The appropriate EMC rules are selected for the application and applied during the design phase, such as a DRC check.

EMC Adviser’s guidelines provide design issue recommendations, enabling non-expert users to solve Signal Integrity, Power Integrity, and EMC issues. Users can choose and configure from 36 rules in 6 categories, generate check results, cross-select, and highlight within the PCB layout, and create summary reports.
Summary reports with images and progress status can be shared as MS-Excel documents between the members of the development team. There is no need for any additional software to verify the identified EMC issues.

singal integrity, power integrity and emc issues

Rule categories and checks

  • Are there any closed loops in my design?
  • Are there any unintended open critical loops?
  • Does any long track act as antenna?
  • Are there any isolated copper shapes?
  • Are any high-speed signals routed close to the edges of reference planes?
  • Are there enough Vias spent along copper shapes to avoid effective antennas?
  • Is there a potential to create current loops within copper shapes?
  • How is the coverage of shielded signals?
  • Is there any vertical shielding in Z-axis?
  • Is any shielding missing in 4 directions (left/right/above/below)?
  • Is the shield continued across Vias?
  • How is the shielding coverage of defined net groups?
  • How is the ground coverage beneath a component?
  • Is the return path too far away from my high-speed signal?
  • Are there any areas with high Via density? Identify cutouts and gaps caused by overlapping anti-pads.
  • Is there a unique reference signal assigned to the high-speed signal?
  • Is the lowest inductance path used for return currents between the boards? (Multi-board)
  • Is there any impedance mismatch in critical signals?
  • Is it necessary to add a specific termination to the high-speed signal?
  • Find all 90-degree corners in my design
  • Check all signals for critical line length
  • How is the routing quality of differential signals?
  • How large is the track capacitance? Is the maximum capacitive load exceeded?
  • Check for crosstalk between active and passive signals
  • Check for crosstalk between active signals and power nets
  • How effective are the used EMC components?
  • Is a signal marked for ground prohibition close to a ground net (same layer or adjacent layer)?
  • How strong is the noise coupling between multiple boards? (Multiboard)
  • Are Decaps too far away from the IC power pin?
  • Are there any overlapping power planes that acts as noise bridges?
  • Are any connectors affected by high-speed signals running over gaps?
  • Are there any high-speed signals routed near a Via of a power net connected to a connector?
  • Check the track width and number of Vias between the pin pairs
  • How good is connection path length of used ESD components?

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