What’s New in CR-5000 Revision 18
CR-5000 revision 18 offers a number of workability and operability enhancements to improve product delivery schedules and reduce costly, error-prone steps in the design process.
In addition to the features highlighted below, further information is available in the product release notes.
- Enhancement of Area DRC
- Improved Equi-space Via Generation
- Enhanced Test Point Features
- Enhanced Area Design Rule Checks
- Enhanced Differential Pair Routing & Checks
- Enhanced Differential Pair Routing Move
- OBD++ Output Function Improved
- Display Pin Names and Part Names
- Extended LCBD Extraction Function
- Lightning Linkage Enhanced
- DFM Center Check Items
A portion where a hole scrapes a conductor or breaks a line can now be detected.
Further work to delete vias that overlap a component terminal or an existing via is no longer required.
More efficient test point design
Curved segments or arcs with a common center point, are generated to maintain spacing between the wiring.
Enhancement of Area DRC
Any portion where a landless pad stack and a line pattern overlap within the same net can now be detected.
Improved Equi-space Via Generation
Vias where the clearance between them within the same net cannot be maintained will no longer be generated. This offers more efficient power supply plane design.
Enhanced Test Point Features
Test points on a net with the test point count set to zero in the net rule can now be detected.
Enhanced Area Design Rule Checks
A new mode in the Area DRC offers the option for no stack via errors to be generated for “via hole” clearances.
Enhanced Differential Pair Routing & Checks
For a set of bends on differential pair wires, tangent arcs can now be generated for all bends simultaneously. No further work is required to specify, delete and assign fillets with the edit line command.
Arcs are now included in calculations during clearance and parallel ratio checks for differential pair routing. The length of sections where wire spacing is both consistent and inconsistent is now reported.
Enhanced Differential Pair Routing Move
The center between a differential pair wiring can now be snapped to a grid.
OBD++ Output Function Improved
- User-defined attributes appended to a part of a component can now be output to ODB++.
- Drill layer output order may now be specified.
- MISC layers that have been excluded from output are no longer created
Display Pin Names and Part Names
Pin and net names may always be displayed, in the same way as a pin number. This means it is easier to see what signal exists on each pin and review boards with high pin count components such as PGAs, in which pins are frequently swapped. More efficient wiring is achieved as the cursor does not need to be placed on pins.
Extended LCBD Extraction Function
More detailed design rule checks can be made as clearance values can be checked separately against the same and different nets
User-defined attributed of a part with pin assignment set now take precedence over user-defined attributes of a pin for the pin assignment when being passed to the LCDB. This gives more flexible operation in the circuit verification environment.
Lightning Linkage Enhanced
Simulations that refer to elec_type or enetSeries for a component on a circuit are now also enabled for variant components.
DFM Center Check Items
Clearance(same net) and Clearance(different net) have been added to the check methods. This allows separate checks for clearance values within the same net, and clearance values in different nets. This allows more detailed checking of designs.