Integrated Environment for Designing PCBs, BGAs and MCMs
CR-5000 Board Designer
Zuken's CR-5000 Board Designer provides an intuitive, integrated environment for designing PCBs, BGAs and MCMs. It serves to guide the user, via a common user interface, from circuit design through to floorplanning, placement and routing, analysis and into manufacturing. Rules are constant throughout the design process and are dynamically linked to ensure flexibility and consistency.
- A single, intuitive environment with a coherent approach throughout the design process, easy links between tools, and a common database and libraries
- Rules-driven design for correct-by-design outcomes
- An optimized combination of automatic, semi-automatic, and interactive functionality to maximize design productivity
- Design partitioning facilitates intelligent, concurrent engineering; especially useful for large or complex products and for the re-use of proven circuits
- Re-use of proven circuit blocks saves time
Floor Planning and Routing
This tool enables floor planning of individual components and groups of components, taking account of the side of the board on which they are to be placed. This information, together with both component and net information is linked with Design Gateway.
Wiring input is made easier because fillets and tangent arc shapes can be generated simultaneously. Real-time spread is supported for wiring and surface shapes. Online design rule checking (DRC) takes account of resist patterns and ensures equal-potential nets.
Unconnected nets can be automatically detected and selected during interactive routing. Additionally, an automatic bus wiring and editing function identifies those nets that are suitable for bus wiring in advance, simplifying bus input operations. Placement and wiring information can be automatically copied and placed elsewhere in the design. Move components with indicators guiding users for optimum location and dynamically consider the virtual wiring length during placement. Component push and rewiring after placement are also supported.
Components can be grouped together and, by creating a group region, preliminary placement and component DRC checks can be carried out, taking account of wiring blocks.
All data assigned to nets and components are confirmed in real-time using a dialog display. Furthermore, maximum and minimum wiring length limits are displayed in graphical form during wiring and relocation.
Net density is displayed in real-time when wiring after component placement. The degree of detour can be specified in the calculation of virtual net lengths, and this allows checks to be made in conditions where actual wiring is assumed to have been carried out. Additionally, net density is constantly checked while components are moved.
Even when there is no indication of bypass capacitors on the schematic diagram, batch generation can be carried out in the vicinity of the corresponding IC. Batch generation is also available for fillets, shield patterns, surface patterns for reinforcement, and the like. Detailed parameters that specify factors such as the arc radius and connection component can be set. Supplementary vias that are effective in lowering the impedance of power supplies and grounds can be batch generated and a myriad of dimension line patterns can be created for length, diameter, angle, lead, etc. Positions, arrow shapes, and repeat input can also be specified.
Gerber data, HP-GL/HP-GL2 format plotter data, layer data from separate PCB files, and similar information can be read during interactive design.
By defining regions on a PCB and dividing them with connection information intact, multiple designers can work on each region. Furthermore, the consistency of the board's design information is maintained. Partitioning in copy mode is also supported. Design File Manager presents the partitioned data using a hierarchical display. Monitoring functionality allows designers to view other files currently opened by other engineers. During division, connectors that indicate the connection points for partitioned sections can be generated.
Upon expansion, it is possible to specify a wide range of different options relating to, for example, the integration of surfaces, the preservation of land conditions, and the layers to be expanded.
Build-up technologies that reduce layer count and improve board density are supported through dedicated commands in combination with libraries of layer configurations, vias, and clearance rules. The Build-Up Rule Editor is a dedicated visual editor for setting via and clearance rules for build-up boards. Additionally, a double via checking function enables correct generation of double vias for connection reinforcement or improving current carrying capacity. An optional, web-based service provides a library file of layer configurations, vias, and clearance rules for the build-up board specifications from a variety of board manufacturers.
Using the 3D Viewer/Editor in CR-5000 Board Designer, vias displayed in 3D format can be moved and modified. 3D Viewer function within BD can be used to change the view of any design at any stage into 3D, thus allowing you to look through the design to see inner layers/complex areas - ideal for HDI/dense multi-layer boards.
Embedded Component Design
This module supports designs with components embedded between board layers. This technique not only saves space but can improve electrical performance, both in terms of signal integrity and EMC performance, particularly in high-speed circuits. Placement sides of the PCB and layer positioning can both be specified while moving components and DRC checks take into account copper foil thickness and insulator thickness. Checks can be performed having set placement side restrictions set for each individual inner layer.
Design rule checking (DRC) extends into component placement in CR-5000 Board Designer. Clearances between components, placement sides, and angular restrictions can be checked. In addition, the maximum wiring length set for a net can be checked at the floor planning stage. Check items have been provided to support the ever diversifying specifications of PCBs.
In-depth checking of equal-potential nets, checked in accordance with the PCB specification, and checking wiring lengths, topology, and other factors necessary for high-speed boards are all supported.
Batch checks can be carried out on resists, silkscreen print elements, and a wide range of other elements relevant to manufacturing data.
Management of check data and referencing of error data is straightforward. Clicking an error report highlights the corresponding PCB area, allowing confirmation to be performed visually. Status information and comments can be added to error data.
Board Designer supports a range of add-on modules including: thermal analysis, using Quick Thermal; advanced floor planning and routing, using Lightning; calculation of optimum die placement, using Package Predictor; and correct-by-design packaging, using Package Synthesiser.
Lightning provides a complete signal integrity simulation toolset, with Constraint Manager at its core. Simulations for analyzing electrical behavior can be started during both schematic entry and board layout. The graphical Scenario Editor provides a scratchpad for experiments with different design strategies, while powerful parameter sweeping helps you to explore design limits and optimize circuit constraints.
Zuken has been at the forefront of routing technology for more than two decades . A combination of the world’s first graphical grid-free routing algorithm technology refined and optimized to deliver 100% routing completion, P.R.Editor XR significantly reduces your design cycle time and increase your productivity providing the options of manual, interactive and automatic component placement and routing capabilities.
Identifying potential problems at the earliest stage possible minimizes the possible negative effects of design changes, reduces the overall development costs and speeds-up the design cycle.
Rules are defined into categories to allow engineers to check the design and provide guidance and advisce to avoid potential problems.
Power Integrity Advance provides fast and practical power integrity (PI) and electromagnetic interference (EMI) analysis embedded within CR-5000 Lightning, during PCB layout, within your real-time PCB design flow.
XDF Viewer is a web browsing tool that allows departments to conduct design reviews with mark-up capabilities and import design rule check results.
RF Physical Design and Verification
CR-5000 Board Designer can be linked with ADS, Agilent Technologies' RF high-frequency design tool, for the realization of high quality boards containing both baseband and RF circuits. The tool provides layout data conversion in which distributed constant circuits are created by converting lines into transmission line components. Conversion to surface data for use in electromagnetic field simulation is also supported.