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It’s 25 years since the first FED Conference took place in Berlin back in 1993, as a gathering for the German-speaking electronic and PCB-related industry. This also happened to be the year we consider as the birth of high-speed design.
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Have you ever finished generating the manufacturing release package for the latest product design and then it occurred to you that something may be wrong? Imagine, it’s Thursday night and you just finished a nice dinner with the family. Your daughter’s soccer team won and the Broncos are playing the Chiefs tonight. It will be great to relax and enjoy the game.
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DDR4, the fourth generation of DDR SDRAM technology, is the latest and greatest SDRAM standard and will continue to be until the fifth generation is released. The new standard features a point-to-point architecture that offers superior timing margins.
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Defining initial hardware architecture requires many decisions, most of which impact a variety of different stakeholders and requirements – including multiple design tools – circuit design, PCB layout, mechanical design, spreadsheets, etc. that are used to track different elements of the design.
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After a lengthy quiet period, the hardware design process is suddenly experiencing numerous changes in the form of design discipline convergence and process extension. The widely used 2D single board PCB detailed design process is being replaced by a 3D multi-board and multi-discipline one.
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The PCB design team at Renishaw work with flex PCBs and flexi-rigid boards that require detailed signal integrity analysis. To achieve the most accurate results they are working with Zuken’s electronic PCB design software to visualize boards in 3D using imported MCAD data. This also ensures that sure high-speed digital signals can be transmitted with minimal distortion.
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I recently talked on predictive failure analysis at the PTC LiveWorx 2017 conference. There was a lot of audience interest, so I thought I’d share some of the things I discussed. This is the second of two posts on this subject.
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I recently talked on predictive failure analysis at the PTC LiveWorx 2017 conference. There was a lot of audience interest, so I thought I’d share some of the things I discussed.
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No more distractions, please! 45% of our time is already spent on admin. If you’re the average engineer, that is.
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With key functionality in many cases commoditized, the success or failure of wearables is increasingly determined in the early stages of the PCB and mechanical integration process where requirements are translated into practical design decisions such as how functions are mapped to PCBs and PCBs are integrated into the enclosure.
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In the final installment of this blog series, you can learn how to use build-up layers and premium FPGAs to deal with the signal integrity challenges arising from high-speed signals in a 3D design capture world.
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This is the second in my series of blog posts looking at the challenge of maintaining PCB signal integrity with now-common ultra-high speeds and growing adoption of PCB design environments to design in true 3-D. Today I focus on vias and the use of return vias to overcome the issues highlighted in Part 1.
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Ultra-high signal speeds demand detailed consideration of the third dimension in PCB design, including via structures and layer stacks. Today I’m going to focus on the challenge. In my two subsequent posts I’ll be reviewing what PCB designers can do to meet that challenge.
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In my previous post in this series about effectively reusing design modules to increase product quality and decease development time, I challenged you to think about how well you’re making use of existing design modules and why getting better at this could be a competitive differentiator.
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In this two part series of blog posts, I’m going to be looking at reuse with modular design in PCB development, and how you can streamline your methodology to reduce design time, reduce design errors and increase product quality.
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As companies benefit from the global supply chain in terms of lower production costs and faster turnaround times, they are also exposing their intellectual property to third parties, including PCB design data.