Return Vias, Build-Up Layers and the Latest FPGAs to Battle Latest Signal Integrity Challenges

Return Vias, Build-Up Layers and the Latest FPGAs to Battle Latest Signal Integrity Challenges


In the final installment of this blog series, you can learn how to use build-up layers and premium FPGAs to deal with the signal integrity challenges arising from high-speed signals in a 3D design capture world.

Placing return vias

Placing return viasLuckily, where signals need return vias, component vendors often do most of the work for you. Let’s look at a PCI Express differential pair.  First, the standard connector, showing its pinout but not its body; I’ll cover the connector body in a moment. The signal pin assignments are also standardized.

This one is a through-pin component. The two sides of the differential pair (I’ve marked them P and N), are close to ground pins. There’s some differential coupling between the P and N pins and the ground pins create returns in the Z dimension, just like ground planes do for traces.

The connector body works in a similar way. Here’s a small area of the connector, mounted on its footprint. Inside the body, the differential pair has ground metal each side.

Small area of the connectorSo you can already route this pair from BGA to connector on, say, top and bottom layers, without adding any other vias. If you really need another layer change for a signal like this, then you have to decide on signal via-to-via and return via spacing.

Or do you?

Let’s look at the BGA itself. In this case, its balls are on a 1mm grid, fanned out to vias at even spacing. I’ve added markers on the vias to show the differential pair (N and P) and surrounding ground vias. These signals are on a special high-speed transceiver bank on the FPGA. If you need another layer change, then one way to decide on spacing is just to copy this pattern.

Alternatives to return vias

BGAYou can’t backdrill vias inside the area of a BGA like this, so the alternatives are blind vias or build-up layers. In any case, you often need build-up layers to achieve the high route density that BGAs like this demand. All that’s required then is to restrict routing layers.

  • Build-up vias are also much smaller than conventionally-drilled vias and their correspondingly smaller parasitic resistance, capacitance and inductance yield better performance even on slower signals.
  • Blind and buried vias add process steps and expense.
  • Backdrilling is mainly suited to larger via geometries, so its use is limited, but it’s effective for signals that are a little less critical than PCI Express, such as some SDRAM buses.


Premium components like the FPGA mentioned here include features to help signals fly true. Some of the latest BGA footprints are so fine-pitched that many signals connect through via-in-pad to inner layers only with no room for tracks between pads.

Now that EDA environments work in three dimensions and with high levels of detail, it’s much easier to visualize where signals are going and what will help or hinder them.


Also See:

Jane Berrie
Jane Berrie
Electronic Design Technology Partner
Jane Berrie is an EDA product innovator and technical marketing content creator, focusing on high-speed design and signal integrity. She is a published author of technical articles and a past session chair at the annual Design Automation Conference (DAC). Jane enjoys managing themed charity events, disco and going out with friends.
  • Blog
May 06, 2024
Addressing the Skill Shortage in PCB Design with AI

As we face a skills shortage many areas of eningeering, more and more engineers are finding themselves in roles that require skills they may not have been trained for. But what if we could use AI technology to help close this gap? Learn more.

Read now
Reuse of Schematic and Layout Modules in PCB design
  • Webinar
April 12, 2024
Dealing with Component Obsolescence in PCB Design

This webinar will demonstrate how Zuken's CR-8000 Enterprise PCB Design System automates updates and redesigns in response to component obsolescence. Learn how to identify affected modules, update designs with a schematic module library, and intelligently assist layout modifications.

Live Webinar on June 11, 11 am CEST
Abstract visualization of a brain-shaped printed circuit board, depicting the concept of artificial intelligence in PCB design
  • Blog
January 11, 2024
Harnessing the Power of Artificial Intelligence for PCB Design

With the release of ChatGPT, artificial intelligence, has become a topic that has stirred many emotions. On our blog we're exploring whether AI could one day be used to support Zuken's core business of solving complex design challenges such as PCB layout and routing.

Read now
Detailed view of a DDR4 memory module, highlighting intricate circuit patterns and metallic connectors indicative of high-speed data processing capabilities.
  • Blog
December 04, 2023
DDR4 Design Masterclass: Advanced Techniques for Optimal Memory System Design

Although memory technology continues to evolve, in the current technology landscape, DDR4 is often a critical hurdle in the design process of an electronic application because of the large number of rules and constraints which have to be obeyed for the implementation of high-performance memory subsystems. Learn what to consider.

Read now