Zuken CR-8000 2020 Release

CR-8000 Release 2020

System-Level Engineering and Physical Design Efficiency

Key Development Themes

Zuken reveals details of release 2020 of its advanced 3D multi-board EDA environment CR-8000. Key development themes for CR-8000  2020 are

  • Superior Design Efficiency
  • System-Level Design and Embedded Verification
  • Support for Advanced Packaging Technology

Many enhancements contained in the new release were developed in close collaboration with Zuken’s global customers in business sectors, including electronics, high tech, automation, automotive, aerospace, and defense. As product complexity increases, these businesses are searching for opportunities to increase design performance and process resilience. 


Key Theme: Design Efficiency

Major enhancements in the areas of schematic design, FPGA optimization, skew group routing and support of back drilled vias. Streamlined routine design work through extended semi-automatic routing functionality.

Design Gateway, the schematic capture and engineering environment of CR-8000, has been significantly enhanced by the move to a native 64-bit environment for improved rendering and performance, and the introduction of a new (Windows 10 style) graphical user interface that has been designed to provide enhanced usability and performance.

The new graphical user interface of CR-8000 Design Gateway

A redesigned Design Tree View improves navigation in large designs. In addition to the hierarchical representation of folders and sheets, the Design Tree View now includes a design resource folder which contains a detailed history of output files (such as netlists and BOMs) and logs files documenting the full design history,  as well as a listing of the specific design rules applied in the current design.

Re-designed Design Tree View in Design Gateway

Board designers can now perform FPGA gate and pin swaps directly in Design Force, the board layout, and routing application of CR-8000. All changes made in Design Force will now be automatically back-annotated to Zuken’s FPGA and board co-design environment Graphical Pin Manager.

FPGA gate and pin swaps can now be performed directly in Design Force

Extended use of semi-automatic routing provides significant efficiency gains by streamlining the time-consuming task of optimizing signal lengths for skew control. Signals can be highlighted automatically in color codes to indicate their compliance with the skew constraint defined in the circuit design. Green indicates ok, red indicates too short and blue indicates too long. In this way, skew violations can be easily identified and addressed by increasing or shortening tracks lengths using Design Force’s sophisticated routing tools.
Optimization of signal lengths for skew control in CR-8000 Design Force

To reduce potential antenna effects of unused plated vias in high-speed boards, Design Force has been enhanced to automatically identify via stubs for back drilling during board production. Drilling data for back drilling vias can now be generated in a one-stop operation during board layout eliminating the time-consuming task of manual identification and generation of drilling outputs.

Drilling data for back drilled vias can be generated in a one-stop operation during board layout with Design Force.

Routine design work benefits from the extended availability of semi-automatic functionality. The component placement functionality has been extended to include automated push aside algorithms that make room when components are added; for dense areas, track widths can automatically be reduced to user-defined values. Moving between active layers is now made easier by using the upward and downward key.
The placement functionality of CR-8000 Design Force has been extended to include automated push aside algorithms for components

Key Theme: System-Level Design and Verification

Optimized electro-mechanical design flow for flex-rigid PCBs and directly embedded multi-domain analysis capabilities

Geometries and dimensions can be directly imported from all industry-standard MCAD design tools. Mechanical outlines are automatically extracted by Design Force and the PCB design data updated automatically.

Using the Design Force’s 3D design capabilities, flex parts can be manipulated and checked for interference and clearance directly in the PCB design environment. Inversely, updated, and verified flex PCB date can be exported back to M-CAD.

PCB data can be updated in Design Force with the shapes of rigid and flex boards imported directly from MCAD data

Direct integration of best-in-class analysis solutions from Zuken’s partners Keysight and ANSYS enables the analysis of PCB designs across multiple domains. Various techniques of simplifying board design details data have been introduced to reduce the time for meshing and contribute to stabilizing simulation results.

2.5D and 3D data can be transferred directly from Design Force to the Keysight RF design and analysis environment, where the layout characteristics can be extracted and optimized in a what-if-approach.

Similarly, ANSYS simulation tools for signal integrity, power integrity, and EMC as well as electromagnetic field analysis, thermal analysis, and structural analysis can now be launched directly from the CR-8000 environment.

Embedded solutions from Zuken’s partners ANSYS enable the multi-domain analysis of designs in CR-8000 Design Force

Key Theme: Support for Advanced Packaging Technology

To cover the latest advances in the area of packaging technology, CR-8000 Design Force has received additional as well as enhanced functionality in the areas of tile bump planning and 3D wire bond design for power modules

The bump design for Flip Chip Package (FCPKG) designs needs to consider both system-on-chip and package design constraints to establish an optimal solution in an iterative process. Using today’s industry-standard design tools, it is difficult and time-consuming to run many iterations, as changes need to be coordinated between the different tools with the help of spreadsheets. With hierarchical multi-domain capabilities in an end-to-end environment, Design Force supports both the design of individual packages and boards, and a concurrent implementation and optimization of  chips, packages, and boards.
CR-8000 Design Force Flip chip with redistribution layers in native 3d - Chip Package Board
View complex designs in native 3D – example: Flip-chip with redistribution layers

Due to the growth of the IoT and connected devices, the demand for power modules is projected to grow drastically. Power modules are placed as ceramic child boards on a baseboard and connected by means of 3D bonding wires. With today’s design tools, designs using power modules frequently involve disconnected tools, with the wire connections frequently being designed on M-CAD tools. By supporting 3D multi-board co-design and SiP (system-in-package) wire bond designs in one consistent environment, CR-8000 Design Force 2020 provides a consistent environment for the system-level design and verification of power modules

Support for complicated 3D wire design and competitive edges in collaborative analysis