SemIsrael Virtual Technology Week 2020

June 15th - 17th
COUNTDOWN TO SemIsrael Virtual Technology Week 2020

Zuken’s presence at Semisrael Virtual Technology Week 2020

SemIsrael Virtual Technology Week features a per-topic, segmented and focused online conferences. Each conference is uniquely tailored for its target audience, with right agenda and mix of exhibitors.

SemIsrael Virtual Technology Week 2020 includes three semiconductor topics:

  • IP & Cores
  • Test & Package
  • Front-end Design & Verification


Here’s why you should attend SemIsrael Virtual Technology Week 2020:

  • Join Online and meet the who’s who in your field of expertise
  • Get the most updated current technology and know-how from leading vendors
  • Best networking event
  • Enjoy the unique quality of SemIsrael professional events

Semisrael registration

10:10 IST (GMT + 3:00)

Iyad Rayane is an application engineer at Zuken focusing on the Co Design flow and Advanced Packaging solution with CR-8000. He holds an engineer diploma and a Master’s degree in microelectronics from the poly-technical institute in Grenoble, France. He has more than 20 years of experience in the semiconductor field where he worked around 11 years as application engineer at Mentor Graphics for SoC design on advanced process nodes. Prior to Mentor Graphics, he worked as EDA engineer at ST Microelectronics developing RF and mixed signal design flows for big design houses. Iyad started his career in a startup in Grenoble area specialized in the Mems design and modeling. He is author and co-author of many scientific publications in international conferences.

10:10 IST (GMT + 3:00)

The demand of consumer electronics and mobile communications devices drives electronics manufacturers to deliver more and more compact and portable devices. Today we require more features, better performance, earlier and smaller. All these requirements are driving semiconductor companies to develop new IC packaging technologies to provide greater integration in smaller packages.

The last decade has seen an explosion of new packaging technologies including FOWLP, stacked IC packages and SiP. Designing those packages typically involves three independent design processes – chip, package and PCB – carried out with point tools whose interface requires time-consuming manual processes that are error-prone and limit the potential for reuse. This challenge is being addressed by a new integrated 3D chip/package/board co-design environment that streamlines the best SiP implementation by considering the system-level impact of each design decision, especially for optimizing. The new co-design approach enables netlist management to follow up design modification including die partitioning and seamless electrical characteristic verification during the design. The end result is higher performance and improved quality for smart systems, MEMS and IoT applications.


If you have any questions, please contact the Zuken event manager Francesca Libe. Email:

Zuken @ SemIsrael


Register Now