High Speed Design Demystified: LPDDR4 Design Explained

A Guide to mitigate Low-Power DDR4 Design

A trend towards low power design prevails in the electronics industry today and is not likely to change in the near future. This development is driven by many reasons but primarily by the performance and storage density demands of mobile devices, where a reduction of the power consumption is crucial to extending battery life without sacrificing the bandwidth.

However, low power DDR memory is now spreading to other industries such as industrial automation and the automotive industry as well. Electromobility is seen as the key to climate-friendly mobility and innovation worldwide, but it requires a high level of energy efficiency in all electronic components on board, which ultimately all require energy from the battery. This ongoing trend poses new challenges for PCB designers as data rates exceed multiple giga-transfers per second and timing margins are shrinking further with every memory generation.

High density for small form factors

LPDDR, an abbreviation for Low-Power Double Data Rate is a type of memory that operates on a lower supply voltage level (compared to regular double data rate memories) and consumes less power. It was initially targeted for smartphones, tablets, and other smart connected devices that facilitate the industry 4.0 with its cloud applications and big data. In other words, the here discussed LPDDR4 is the mobile equivalent of DDR4 with a higher memory bandwidth and a reduced voltage level and with some minor other functional differences. Interestingly, its share of the total memory market has been growing over the past years, so it’s not unlikely that it will show up in one of your next bill of materials.

lpddr4 voltage, lpddr4 bandwidth
Source: jedec.org

What are the challenges in design and validation?

Following the framework of the JEDEC standard JESD209-4C, the relevant rules and constraints for LPDDR4 memory devices and their usage have been adopted by all semiconductor vendors. This led to more stringent design rules for designers using this kind of memory.

In addition, the form factors of many printed circuit boards are getting smaller and smaller. Therefore, parasitic effects like crosstalk or PDN noise gain importance as trace lines are routed even denser on the board and designers are fighting for every square millimeter and may question every single decoupling capacitor. To add more fuel to the fire, in LPDDR4 design the ICs can be tweaked in a more extensive way compared to DDR3, resulting in many different parameter settings (overshooting, embedded termination devices on driver and receiver side, driving strength and impedance, etc.) that change depending on the design intent. These design challenges are these days quite similar to SERDES in terms of complexity.

Solving LPDDR4 Design Challenges

The tight timing and voltage constraints require a holistic design approach that combines high-speed constraining and integrated analysis techniques to comply with the various design rules. Especially important for design success is a carefully considered pre-layout phase. This should include simulations to find the proper trace width, considerations about the spacing to avoid crosstalk, and calculations to limit the damping and time delay effects of vias in the interconnect path. Careful planning in pre-layout allows design optimization in terms of cost and form factor and to achieve the maximum system performance.

In our on-demand webinar Solving LPDDR4 Design Challenges Ralf Brüning, Product Manager and Senior Consultant for High-Speed Design Solutions, will explain the steps necessary to constrain and validate LPDDR4 using a real-world design that was successfully implemented with CR-8000 Design Force right the first time.

Watch Webinar

Ralf Bruening
Ralf Bruening
Product Manager/Senior Consultant
Ralf works as Product Manager for High-speed Design Systems at the Zuken EMC Technology Center in Paderborn/Germany, responsible for product marketing and business development for the Zuken SI, PI and EMC analysis tools. He holds a diploma degree in computer science, electrical engineering and economics from the University of Paderborn. He has 30 years of experience in Electronics and EDA. He is regular speaker on international conferences, but is involved in European Funding project and standardization activities as well.
  • Blog
February 20, 2023
Sustainable Product Development

On our way to achieving sustainable product development, we ask ourselves one central question: how do we engineer products so future generations have enough resources to prosper? Up to four-fifths of a product's lifetime emissions are determined by decisions made at the design stage. Having all the tools needed to get those decisions right is essential for designing sustainable products that meet performance and quality requirements while using fewer resources across the entire life cycle.

Read now
  • Blog
February 13, 2023
A chat with ChatGPT

Artificial intelligence has been on everyone's lips since newspapers, radio, television, and social media have been overflowing with reports on the AI-based text generator ChatGPT since the beginning of the year. We therefore decided to have a chat with ChatGPT itself to find out from artificial intelligence itself what we can expect to see in this area.

Read now
  • Blog
February 06, 2023
Preparing S-parameters/Touchstone® Model for High-Speed PCB Analysis

Learn the history of S-parameters/Touchstone, its advantages and disadvantages, and how to use an automated tool to overcome common challenges in your PCB design.

Read now
  • Blog
January 20, 2023
PCB constraints should drive your design flow. Here's why.

We've all heard of PCB design constraints. They're those little things that limit our ability to create the perfect board in very short periods of time. But what exactly are they? And why do they matter? This blog post elaborates on PCB constraints and why they should drive your design flow.

Read now