Advanced IC Packaging and Co-Design with Design Force
On-demand webinar: Advanced IC Packaging
The demand for consumer electronics and mobile communications devices drives electronics manufacturers to deliver more and more compact and portable devices. Today we request more functionalities, better performance, faster and smaller. All these requirements are driving semiconductor companies to develop new IC packaging technologies to provide greater integration in smaller packages.
The last decade has seen an explosion of new packaging technologies including FOWLP, stacked IC packages, and SiP.
Designing those packages typically involves three independent design processes – chip, package, and PCB – carried out with point tools whose interface requires time-consuming manual processes that are error-prone and limit the potential for reuse.
This challenge is being addressed by a new integrated 3D chip/package/board co-design environment that streamlines the best SiP implementation by considering the system-level impact of each design decision, especially for optimizing.
The new co-design approach enables netlist management to follow up design modification including die partitioning and seamless electrical characteristic verification during the design. The end result is higher performance and improved quality for smart systems, MEMS, and IoT applications.
What you will learn:
- Latest market trends for IC packaging
- How to solve common challenges in system-level design
- What the system-level co-design approach is about
Presenter: Iyad Rayane, Application Engineer for Advanced Packaging Applications at Zuken