What’s New in CR-8000 2017
Zuken’s CR-8000, the industry’s only product-centric design solution, continues to lead the way with next-generation tools capable of creating today’s and tomorrow’s complex product designs.
CR-8000 2017 is the first release to enhance electrical and electronic co-design at the architectural design phase. CR-8000 improves multi-board system optimization through new module management capabilities in System Planner 2017, and contains more than 150 user-driven enhancements and new features.
CR-8000 is the complete solution for your system-level, single and multi-board design requirements. In addition to the features highlighted below, further information is available in the product release notes.
- System Planner
- ECAD/MCAD collaboration
- Logical visionary connector pair setting (terminal pin assignment)
- Architecture design expands library and modular design support
- Import 3D component shape specified in CDB
- Design Gateway
- DRC and ERC at electrical net level
- Circuit connectivity information list
- Design Force
- Import of MCAD data efficiency improvements
- Bump Line Function for Skew Control
- Support for 3D PDF using PRC
- SI / PI Enhancements
- Improved PI and DC Analysis Flows
- Analysis Result Output in DC Passives
- What-if Analysis Using a Virtual Decoupling Capacitor
- SI Analysis Enhancements
Electrical co-design is added to the architecture design phase through direct export to E3.series, Zuken’s electrical design tool suite. This new capability enables cross-domain architecture optimization, and eliminates the need for data reentry. With the rise in products containing both electronic and electrical design objects, the need for tight design integration across the domains becomes increasingly urgent.
Information on wires between boards can now be output in E3.WDG format. With this process integrated into the system instead of being managed as a manual task, errors may be identified earlier in the design process saving costs and improving quality.
Information on wires between boards can now be output in E3.WDG format.
Logical visionary connector pair setting (terminal pin assignment)
Drawing board or unit connectivity diagrams allow signals between boards and/or units to be studied. Defining the matching pins from the harness pin to the pin connector is done automatically, improving quality over manual matching. Pin pair information can be set for male and female connectors.
Board development diagrams are used for studying signals between boards and/or units.
Architecture design expands library and modular design support
Module and detailed design integration is improved through modular design. Design module status can be verified to detect updates based on a set of user-defined rules. In addition, partitioning a design module across blocks or boards is now possible on a schematic page basis, allowing for improved architectural design optimization.
Reference designator assignments can be made, or auto-generated, during architecture design on a block-by-basis, allowing for more collaboration with detailed design. Design rule checks can also be applied to manage unassigned or duplicate reference designators. During physical optimization, components within the functional block may be identified and moved as a single unit, making floor planning easy and efficient.
The update status of circuit blocks and reused circuits can now be checked.
Import 3D component shape specified in CDB
Geometrical visionary 3D component shapes can be assigned in the library and then imported into designs. This reduces errors compared to the previous manual process.
3D detailed figure information in the component library (CDB) can be imported.
DRC and ERC at electrical net level
Design rule checks (DRC) and electrical rule checks (ERC) at electrical net level check are supported. DRCs now look at one or more electrical nets, offering much more electrically intelligent and robust rule checks.
Change net labels in design from A to B in a single operation
Circuit connectivity information list
The IC connectivity cross reference check function allows the connectivity of the circuit design to be reviewed.
This example shows connection matrix checking considering e-nets.
Import of MCAD data efficiency improvements
MCAD co-design has been expanded by importing figures from a board model created using mechanical CAD. Supported systems include CATIA V5, Creo, NX, SolidWorks, STEP, Parasolid, and ACIS. More accurate and speedier designs are possible using this level of mechanical detail.
The following data can be imported to design data: Board outline; Hole (Round hole, slot hole, rectangular hole, non-circular hole); Height limit area, area fill; Arrow view from the top or bottom of a component shape; Component coordinates.
Improved creation of PCB design data from mechanical CAD data.
Bump Line Function for Skew Control
Skew adjustment control is possible using ‘bump line’, both in style and type, while maintaining impedance differential.
- Enhancements made to the Edit function
- Improvement to efficiency in skew adjustment for route differential pairs
- Additional function to delete all, or selected bump lines
Skew adjustment control is possible using ‘bump line’
Support for 3D PDF using PRC
Enhancements have been made to the 3D Model Export function to allow export of PRC data for subsequent output as a 3D PDF using third party software.
3D Model Export function exports PRC data for subsequent creation of 3D PDFs using third party software.
SI / PI Enhancements
Improved PI and DC Analysis Flows
Enhancements to the PI/EMI Analysis Tool include a refreshed GUI and streamlined workflows improving the efficiency for PI and DC analysis.
Refreshed GUI and streamlined workflows improve PI and DC analysis efficiency.
Analysis Result Output in DC Passives
Analysis results, such as voltage drops, are now measured and shown on passive device ports explicitly similar to other DC analysis results.
What-if Analysis Using a Virtual Decoupling Capacitor
A decoupling capacitor can now be virtually added without changing the circuit configuration, making selecting the decoupling capacitor more efficient.
Voltage drop, current and power consumption values of each passive device can be viewed.
SI Analysis Enhancements
- TDR (Time Domain Reflection) analysis conditions can now be set, which makes providing verification of all variations easier and smoother.
- If no IBIS models are available, device models as templates for simulation can now be created using information on components/parts on a board, greatly reducing the time and effort to assign and define information for SI analysis.