{"id":2324,"date":"2011-03-24T12:22:02","date_gmt":"2011-03-24T16:22:02","guid":{"rendered":"http:\/\/zukenblog.wpengine.com\/?p=2324"},"modified":"2023-05-12T13:19:09","modified_gmt":"2023-05-12T17:19:09","slug":"how-to-overcome-design-challenges-associated-with-gigabit-signalling-and-the-ubiquitous-lvds-in-high-speed-pcb-design-part-2","status":"publish","type":"post","link":"https:\/\/www.zuken.com\/us\/blog\/how-to-overcome-design-challenges-associated-with-gigabit-signalling-and-the-ubiquitous-lvds-in-high-speed-pcb-design-part-2\/","title":{"rendered":"How To Overcome Design Challenges Associated with Gigabit Signalling and the Ubiquitous LVDS in High-Speed PCB Design (Part 2)"},"content":{"rendered":"

In the first part\u00a0\u00a0I covered just the bare essentials of why Low Voltage Differential Signalling (LVDS) is so popular<\/a>.\u00a0 So what\u2019s important about how these high-speed differential signals are routed, and why?<\/p>\n

I\u2019m going to focus here mainly on PCI Express, but the differential routing considerations apply equally to other LVDS technologies and to differential routing in general.<\/p>\n

Routing PCI Express<\/h2>\n

As a reminder, each PCI Express Lane <\/em>is Dual Simplex, as shown here. Each differential route goes from a differential driver to a differential receiver. There is always a terminator between the + and \u2013 sides of the pair, because LVDS is a current loop technology (see Part 1).<\/p>\n

So what\u2019s important to consider when routing signals like this?<\/h2>\n

Recalling from Part 1 that PCI Express encodes clock with data, then skew (differences in route length and delay) between one lane and another isn\u2019t so critical. In technologies that keep the clock separate, like HyperTransport, other types of skew remain a critical consideration.<\/p>\n

How about skew between the two simplex differential pairs within<\/em> each lane? Well it isn\u2019t essential to match transmit and receive within one lane but the inescapable logic of symmetry applies, as for skew between lanes, and the same remedy will work well here.<\/p>\n

So we are left with skew within each differential pair. In fact, I don\u2019t like the word \u201cskew\u201d in this case, because a parallel-routed, coupled, differential pair is one signal, not two.<\/p>\n

Here again, innovative hardware is taking some of the complication out of routing and in some cases can even adapt to board characteristic impedance variations, compensate for signal loss and introduce delays to compensate for skew.<\/p>\n

The Lowest Common Routing Denominator<\/h2>\n

Whatever signal integrity compensation is included in devices, one exacting routing issue remains; you must match the routing of the two sides of each differential pair precisely. This requirement applies to all multi-gigabit-per-second differential technologies. It isn\u2019t sufficient to match the length of the + and \u2013 sides; if it were, then the hardware would be able to compensate. You need to phase-match within a very small tolerance. On one of the point-to-point simplex differential pairs I talked about earlier, you need to start routing at the driver (transmitter) and deviate as little as possible from the recommended track-to-track spacing, making sure the route length from the two driver pins stays as near equal as it is possible to be over the entire length.<\/p>\n

The \u201cDifferential Impedance\u201d used to calculate the bridge terminating resistor (often on-chip and 100\u03a9) at the receiver end relies on this precise matching of route length. \u00a0The impedance is only matched accurately by the terminator when one signal is precisely inverted with respect to the other at every point in the routing; otherwise, the impedance will be different. I will cover mode impedance<\/em> in a later blog, because it\u2019s a big subject in itself. For now, please take a look at this picture, which represents the field lines between the + and \u2013 halves of a differential pair route. Notice how the field lines are pulled together between the two halves. That only happens if the signals are completely complementary and if it doesn\u2019t happen, all bets are off.<\/p>\n

For common PCB layer stacks, the application notes for devices such as Field Programmable Gate Arrays (FPGAs) often recommend track-to-track separation within each pair and between one pair and another. It\u2019s very important to maintain these separations and symmetry of items such as vias and test points throughout the routing so that the travelling wave on one side of the pair isn\u2019t altered in a different way from its partner on the other.<\/p>\n

You still need to simulate, because coupling and variations in ground and power planes can easily knock out the intended operation. For high-speed buses like these, it\u2019s usual to simulate eye patterns to make sure the signals behave reliably for a long, pseudo-random data stream.<\/p>\n

In Summary<\/h2>\n

I\u2019ve only skimmed the subject of Gigabit Signalling and LVDS here and I\u2019ve focussed on the lowest common denominator in routing. I\u2019ve not mentioned much about simulation, eye patterns, coupling effects, power integrity and all the rest of that, because I need some material for future blog posts ;-). For now, I need to get back to reading some specifications, so until next time …<\/p>\n","protected":false},"excerpt":{"rendered":"

Recalling from Part 1 that PCI Express encodes clock with data, then skew (differences in route length and delay) between one lane and another isn\u2019t so critical. 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