{"id":10610,"date":"2016-02-23T18:13:53","date_gmt":"2016-02-23T18:13:53","guid":{"rendered":"http:\/\/zukenblog.wpengine.com\/?p=6893"},"modified":"2023-05-13T03:56:19","modified_gmt":"2023-05-13T07:56:19","slug":"iot-makes-complex-design-problems-mass-market-part-2","status":"publish","type":"post","link":"https:\/\/www.zuken.com\/us\/blog\/iot-makes-complex-design-problems-mass-market-part-2\/","title":{"rendered":"IoT Makes Complex Design Problems Mass Market – Part 2"},"content":{"rendered":"

\"\"In the first part of this blog series (here<\/a>), I looked at the explosion in the growth of internet connected technology and wearable devices, and started to look at what kind of design challenges this posed; not just for cutting edge niche products, but mass market general electronics goods.<\/p>\n

I started to explore the need to collaborate on a mechanical level; but the level of integration really needed to compete in this space goes far beyond that.<\/p>\n

Cross-discipline collaboration<\/h3>\n

This shouldn\u2019t be limited to PCB and mechanical disciplines – there\u2019s a need for collaboration across the system. Traditionally, the PCB, package, IC and enclosures are each designed in their own stand-alone 2D environment. With increasing functionality, tight schedules, tighter cost constraints, and the decreasing form factor of today\u2019s IoT and wearable products, components need to be tightly coordinated with one another so that pin assignments can be optimized for small size and minimum layer count substrates. The overall goal is to align the boards, packages and chips so that signals follow the shortest possible path in the fewest layers possible from the chip through the board to the chip, resulting in the fewest possible layers across all substrates.<\/p>\n

\"\"
Managing complex 2.5\/3D package interconnect with TSVs<\/figcaption><\/figure>\n

It\u2019s important now to be integrating detailed design using PCBs, packages and ICs, within their mechanical enclosure.<\/p>\n