Eliminate DDR3 Timing Errors with Constraint-based Routing

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On-demand webinar

With DDR3 data rates exceeding two giga-transfers per second, the engineering team needs to employ a constraint-driven design process in order to achieve success. The team must also have the ability to verify that timing margins have been met. The design environment supporting these activities should facilitate the capture and validation of these requirements.

This webinar explores how to realize a DDR3 system using constraints and validate the design’s timing margins. Starting with schematics, we create what-if scenarios, enter constraints, and review initial eye diagrams. Next, we use the constraints to guide placement and routing. Finally, with constraints met, we perform signal integrity analysis and verify that setup/hold margins are honored.

What you’ll learn:

  • Identify length matching rules in a JEDEC DDR3 specification
  • Implement rules as constraints for the DDR3 signals
  • Perform placement and routing per the constraints
  • Run signal integrity analysis
  • Verify setup and hold margins

Who should attend:

  • Design engineers
  • PCB designers
  • Engineering managers
  • Product managers

Presenter

Steven Watt is a PCB Engineering Manager for Zuken USA, Inc. He has more than 25 years of experience in the printed circuit board design industry with an emphasis on IC packaging. Steve has a diverse work background including several EDA companies, Boeing, Motorola, and McDonnell Douglas.

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