EMC problems are often responsible for re-design cycles in PCB design practice. Due to ever shorter innovation cycles of for example cell phones or IoT applications, such as fitness trackers or smartwatches, and many other electronic products, these time-consuming re-design cycles should be avoided under all circumstances.
What do you do if your next project is high speed, with exceptionally stringent EMI requirements, and has to be complete in less time than you’ve ever developed a product before? When the Ontec team found themselves facing that predicament, they turned to Zuken. Why?
CR-8000 2020 is Zuken’s flagship PCB design platform, and I’m pleased to share some of the most exciting details of the new product release with you. But before we get into the new product release discussion, you may be wondering why we call it a platform and not a tool. CR-8000 2020 has all the bells and whistles for electronic subsystem development.
In part 1 of this blog we took a back-to-basics approach and discussed line impedance and its effects in signal integrity. As every electrical conductor comprises capacitance, an inductance, and a frequency-dependent ohmic resistance, and with increasing frequencies, these electrical characteristics will influence and distort the signal.
Impedance and impedance control are some of the oldest and most discussed topics in PCB design. They are especially important in high-speed design related to signal integrity. In this, the first of a two-part blog, we’ll go back to the basics of impedance/impedance control and consider what influences line impedance. In part two, we’ll set about controlling it.
We’re happy to announce that Speedstack, Polar Instruments’ layer stackup design/documentation tools, can now be directly linked to Zuken’s CR-8000 Design Force and DFM Center.
CR-8000 Design Force can help you verify your design before you send it out to manufacture. Before running any signal integrity analysis in Design Force, you must assign device models to the pins in your components using the Constraint Browser.
I don’t think I’m generalizing when I say that designers working on complex high speed designs really don’t want to expend a lot of time and effort dealing with power integrity problems. And they especially don’t want to do it using tools that are detached from their design flow. In today’s complex PCBs, we’re talking advanced processors, complex FPGAs and superfast memories, which all share various voltage ranges.
In the final installment of this blog series, you can learn how to use build-up layers and premium FPGAs to deal with the signal integrity challenges arising from high-speed signals in a 3D design capture world.
This is the second in my series of blog posts looking at the challenge of maintaining PCB signal integrity with now-common ultra-high speeds and growing adoption of PCB design environments to design in true 3-D. Today I focus on vias and the use of return vias to overcome the issues highlighted in Part 1.
Ultra-high signal speeds demand detailed consideration of the third dimension in PCB design, including via structures and layer stacks. Today I’m going to focus on the challenge. In my two subsequent posts I’ll be reviewing what PCB designers can do to meet that challenge.
I’d like to explain to you in straightforward terms what S-Parameters are and why they’re so useful. When I say “straightforward”, I mean that in a technical sense, but this is a specialised area. If you’re not designing high-speed PCBs, or you don’t know much about signal integrity, you might want to tune out now.