CADSTAR 16: Group Handling and Design Efficiency
Zuken Enhances Group Handling and Design Efficiency in CADSTAR 16
14 April 2015 – Munich, Germany and Westford, MA, USA – Zuken, an industry leader in desktop PCB design software, announces CADSTAR 16. The latest version of the price/performance single-board design software contains across-the-board performance enhancements and design efficiency features. These include improved group handling and routing functionality, and enhancements to meet the demands of today’s high-speed designs.14 April 2015 – Munich, Germany and Westford, MA, USA – Zuken, an industry leader in desktop PCB design software, announces CADSTAR 16.
Within CADSTAR Design Editor, users can select and modify items contained within a group, without first ungrouping them.
Driving down design errors is a key way companies can maintain competitive advantage, especially in fast-turnaround designs. This simple enhancement will give users back more time to concentrate on their designs, as well as improving design quality; ungrouping items means risking regrouping them into a different configurationWithin CADSTAR Design Editor, users can select and modify items contained within a group, without first ungrouping them.
Time savings and ease-of-use features
Usability enhancements include:
- Time savings though entering exact length and coordinate values when creating shapes in Design Editor.
- A new hand tool function, offering display panning during execution of commands, such as when moving a component.
- Improved movement of vias in the P.R.Editor Move tool due to enhancement of the pusher and spring-back engine, similar to Activ-45 routing.
- Automatic adjustment of existing lengthening blocks during Activ-45 route and move operations.
- P.R.Editor lengthen functionality now works on individual pin pairs, offering improved overall lengthening results due to improved resolution of skew and overlapping constraints.
High-speed design enhancements
CADSTAR’s P.R.Editor builds on recent enhancements for high-speed design and now supports impedance balanced routing that simplifies the implementation of high-speed interfaces. Engineers can easily route to JEDEC standards and meet DDR3 performance specifications. This reduces design iterations by helping designers optimize circuits for the highest clock speeds.
For more information see www.zuken.com/cadstar
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