What’s new in CADSTAR 18.0
The latest version of CADSTAR meets industry requirements for high-speed design, as well as containing across-the-board performance enhancements and ease-of-use features. These include enhancements for the industry-leading Activ-45 router, making the routing experience even more intuitive and powerful and giving users more control over their designs. More automatic features are available, such as Auto-Assign component copper: a powerful method of connecting pins automatically.
The new CADSTAR Redlining tool helps companies maintain a competitive edge and promotes design quality, by helping engineers of any discipline communicate changes as quickly and accurately as possible.
CADSTAR 18 challenges the view that PCB Desktop software has to be complicated. This philosophy helps maintain CADSTAR's position as the industry’s most-used desktop PCB design software.
For the full details of what's new in CADSTAR 18, please refer to What’s New documentation included with the software.
Productivity and communication enhancements
CADSTAR Redlining: review and mark-up designs
The CADSTAR Redlining tool improves communication between multidisciplinary teams to help companies maintain a competitive edge and promote design quality. Users can quickly mark-up designs during review and easily communicate design issues. These markers can be added to the CADSTAR design without changing the PCB or Schematic. The Redlining marker is a simple item defined by a circular shape and can support the addition of descriptive text, color and line thickness. During production, Redlining enables feedback such as component changes required, to electrical engineers and PCB designers. It also offers a permanent and accurate record of change activity: who carried out changes, when they happened, what was changed and why.
More than two pins can be assigned to one component copper area in the component definition
Enhanced component copper definitions
More than two pins may now be assigned to one component copper area in the component definition within the PCB Design Editor. This makes it faster and easier (using Auto-Assign) to create component definitions that use component copper. New Auto Assign offers a powerful method of connecting pins. Designers draw a copper area on top of window, then choose Auto-Assign to locate and automatically connect the relevant pins.
Users can configure their own back-up options
Support for multiple back-up files
Backup files can now be created with a detailed date and time stamp. The user can choose to save up to 99 backup files, the oldest of which is replaced once a new backup file is created. This offers users more design security, and a greater range of options for replacing lost data and getting back to work faster should issues occur.
Enhanced Activ-45 router
Zuken’s industry-leading Activ-45 router has been further enhanced to offer even faster and more intuitive routing with fewer mouse clicks.
- Flags indicate swappable pins
When routing in single trace Activ-45, the user is now presented with flags to indicate which pins are swappable, which allows easy intervention during manual routing
- Activ-45 Spiral Vias
The Activ-45 manual routing layer change/via insertion has been enhanced to include via spiral insertion, to match the behaviour of the non Activ-45 manual router. This offers increased routing speed.
- Support of teardrops with spiral vias
Fan-out, with both Activ-45 and non Activ-45 manual routing, has been enhanced to add teardrops during spiral via insertion, using the existing Auto Teardrops functionality configured in the Routing Setup dialog. Adding teardrop pads increases the quality of the board during manufacturing.
Flags indicate swappable pins
Spiral via insertion now available in Activ-45 manual routing layer change/via insertion
Add teardrops during spiral via insertion using Auto Teardrops functionality
Signal integrity – support for high speed design
The via_length attribute can be set at the board, net class and net levels
Via length attributes set at the board, net class and net levels
As more applications become high-speed, requiring support for DDR3 and DDR4, it is increasingly important that via length is taken into account. To address this, the calculated minimum and maximum lengths of nets and pin pairs can now include via lengths derived directly from the layer stack within the Constraint Manager found within Zuken's high-speed place and route editor (P.R.Editor XR 5000HS). Also, the via length attribute can be set at the board, net class and net levels. This means that if layers are swapped and via length is added by PCB designers, the information is communicated as early as possible to engineers managing signal integrity. Improved control over net lengths means more control is possible over signal speed for high-speed nets. More closely aligned tools offer better multi-disciplinary communication and, ultimately, improved design quality.
SI Verify enhancements
Accurate impedance definition is always the most important element in achieving successful high-speed designs. Circuit board manufacturing processes, however, have a variety of variable parameters that can influence the final impedance. The Parameter Sweep functions in the SI-Verify field solver now allow users to vary these parameters in the virtual prototype, to determine minimum and maximum impedance deviations.
Parameter sweep of impedance values according to manufacturing tolerances.
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