Zuken has been developing PCB design tools for the automotive market for years. With automotive electronics worth over $200 billion globally, and growing every day, Zuken is preparing for a brave new world of smart cars, and autonomous and electric vehicles.
Simply draw a Dragon area around your BGA. Then select the Dragon area and create a strategy to fanout the pads of your BGA - Watch movie
There is one thing that all design engineers will agree on: creating and gathering all the required data for PLM is error-prone and can be a royal pain. We all understand the value of releasing our design data to the corporate PLM system but our design process dictates multiple release points, and each one has a different purpose and data requirements.
I don’t think I’m generalizing when I say that designers working on complex high speed designs really don’t want to expend a lot of time and effort dealing with power integrity problems. And they especially don’t want to do it using tools that are detached from their design flow. In today’s complex PCBs, we’re talking advanced processors, complex FPGAs and superfast memories, which all share various voltage ranges.
XJTAG has partnered with Zuken create a new plugin for Design Gateway and is offering it free of charge. The plugin, called XJTAG DFT Assistant, helps to validate correct JTAG chain connectivity, while displaying boundary scan access and coverage onto the schematic diagram through full integration with Design Gateway.
Advanced packaging techniques such as system-in-package (SiP), fan-out wafer-level packaging (FOWLP), 3D die stacks, etc. have been around for over a decade, yet with any other EDA design tool, it is still a tedious, time consuming, and error-prone process to implement these designs.
As we witness the birth of an era of connected devices with smart homes, connected cars and smart networked supply chains and factories, we might imagine that unexpected failures of electronic products would be a rarity.
Since it contributed to making the iPhone 7 even thinner than its predecessors, fan-out wafer-level packaging (FO-WLP) technology has risen in the collective consciousness. By adopting FO-WLP on this scale, Apple sent out a signal that though highly novel, the technology had matured.
Because I’ve been in the electrical/electronics (E/E) engineering industry for such a long time, I can still remember drawing PCB layouts manually. We would then work out the connection lengths of wire harnesses by laying out waxed cord lacing on a physical prototype.
Toshiba faced a difficult design problem: their TransferJet™ technology was embedded in a customer cell phone, and when the next rev of the phone came around, they learned that they needed to shrink the board from 8mm x 8mm to 4.5mm x 6mm, and they had to shrink the module thickness from 1.7mm to 1.0mm...
Have you ever finished generating the manufacturing release package for the latest product design and then it occurred to you that something may be wrong? Imagine, it’s Thursday night and you just finished a nice dinner with the family. Your daughter’s soccer team won and the Broncos are playing the Chiefs tonight. It will be great to relax and enjoy the game.
DDR4, the fourth generation of DDR SDRAM technology, is the latest and greatest SDRAM standard and will continue to be until the fifth generation is released. The new standard features a point-to-point architecture that offers superior timing margins.
This is the second in my series of blog posts looking at the challenge of maintaining PCB signal integrity with now-common ultra-high speeds and growing adoption of PCB design environments to design in true 3-D. Today I focus on vias and the use of return vias to overcome the issues highlighted in Part 1.
Ultra-high signal speeds demand detailed consideration of the third dimension in PCB design, including via structures and layer stacks. Today I’m going to focus on the challenge. In my two subsequent posts I’ll be reviewing what PCB designers can do to meet that challenge.
A company’s IP is often the basis for its competitive advantage. Without IP management or protection, your new product can be cloned by a competitor or an unknown third party. IP protection laws vary across the globe so the best approach is to protect your IP before it leaves your company.
As Zuken technology partners, we are often asked about how best to set PCB constraints for double-data-rate (DDR) memory, and how to route to those constraints. This question arose recently when we were asked to create a common style of DDR3 design for training, and we tried mining the web for detailed information on PCB constraints. There had to be something out there, we thought.