{"id":5439,"date":"2013-08-20T09:37:32","date_gmt":"2013-08-20T09:37:32","guid":{"rendered":"http:\/\/zukenblog.wpengine.com\/?p=5439"},"modified":"2023-05-12T14:55:56","modified_gmt":"2023-05-12T13:55:56","slug":"defining-and-routing-pcb-constraints-for-ddr3-memory-circuits-how-to-movies","status":"publish","type":"post","link":"https:\/\/www.zuken.com\/de\/blog\/defining-and-routing-pcb-constraints-for-ddr3-memory-circuits-how-to-movies\/","title":{"rendered":"Defining and Routing PCB Constraints for DDR3 Memory Circuits: How-to Movies"},"content":{"rendered":"<p>As Zuken technology partners, we are often asked about how best to set PCB constraints for double-data-rate (DDR) memory, and how to route to those constraints. This question arose recently when we were asked to create a common style of DDR3 design for training, and we tried mining the web for detailed information on PCB constraints. There had to be something out there, we thought.<\/p>\n<p>We were right; but unfortunately the detail had to be excavated from a vast and comprehensive pile of information about devices and controllers. It was hard to find a brief but clear description of what a PCB designer needs, and why, for a basic DDR3 circuit.<\/p>\n<h2><b>PCB Design of a DDR3 Memory Circuit<\/b><\/h2>\n<p>Necessity being the mother of invention I worked with Kevan Keech, an expert PCB designer, \u00a0to create the most straightforward, realistic example we could think of \u2013 captured in three short movies.<\/p>\n<p>In the first movie I explain the circuit, routing topology and constraints.<\/p>\n<p>In the second movie, Kevan constrains the PCB design.<\/p>\n<p>In the final movie, Kevan routes the PCB design step-by-step and at the end we summarize the results.<\/p>\n<p>We use a single design example from start to finish \u2013 a controller connected to five 1-Gbitx8 SDRAM devices. Levelling is enabled so that the SDRAMs can be routed using fly-by topology, as defined in JEDEC standards\u00a0and elsewhere.<\/p>\n<h2>After watching these movies, you will understand:<\/h2>\n<ul>\n<li>What key routing constraints you need for a memory circuit, such as that outlined in the movies<\/li>\n<li>How to adjust routing to balance impedance of lead-in and loaded sections as specified in JEDEC standards\u00a0and why you might need to do so<\/li>\n<li>How to place SDRAM components for optimum performance<\/li>\n<li>How to constrain the PCB design<\/li>\n<li>How to route accurately to DDR3 constraints<\/li>\n<li>How to ensure constraints have been met.<\/li>\n<\/ul>\n<p>We hope you enjoy the movies and find them useful.<\/p>\n<p>If you\u2019ve taken a look, why not leave a comment below!<\/p>\n<div><\/div>\n<div><\/div>\n<div><\/div>\n<div><span style=\"font-size: 13px; line-height: 19px;\">This blog post was co-written by John Berrie and Kevan Keech, based in the Zuken, Bristol, UK office.<\/span><\/div>\n","protected":false},"excerpt":{"rendered":"<p>\t\t\t\tAs Zuken technology partners, we are often asked about how best to set PCB constraints for double-data-rate (DDR) memory, and how to route to those constraints. This question arose recently when we were asked to create a common style of DDR3 design for training, and we tried mining the web for detailed information on PCB constraints. There had to be something out there, we thought.\t\t<\/p>\n","protected":false},"author":31,"featured_media":11146,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"om_disable_all_campaigns":false,"footnotes":"","_links_to":"","_links_to_target":""},"categories":[228],"tags":[264,15018,265,14243,277],"class_list":["post-5439","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-pcb-design","tag-constraint-management","tag-electronic","tag-high-speed","tag-how-to","tag-routing"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v27.1 (Yoast SEO v27.1) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Defining and Routing PCB Constraints for DDR3 Memory Circuits - Zuken Blog<\/title>\n<meta name=\"description\" content=\"As Zuken technology partners, we are often asked about how best to set PCB constraints for double-data-rate (DDR) memory, and how to route to those constraints.\" \/>\n<meta name=\"robots\" content=\"noindex, follow\" \/>\n<meta property=\"og:locale\" content=\"de_DE\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Defining and Routing PCB Constraints for DDR3 Memory Circuits: How-to Movies\" \/>\n<meta property=\"og:description\" content=\"As Zuken technology partners, we are often asked about how best to set PCB constraints for double-data-rate (DDR) memory, and how to route to those constraints.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.zuken.com\/en\/blog\/defining-and-routing-pcb-constraints-for-ddr3-memory-circuits-how-to-movies\/\" \/>\n<meta property=\"og:site_name\" content=\"Deutsch\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/zukenglobal\/\" \/>\n<meta property=\"article:published_time\" content=\"2013-08-20T09:37:32+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2023-05-12T13:55:56+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.zuken.com\/de\/wp-content\/uploads\/sites\/8\/2019\/04\/pcb-constraints-featured-img.png\" \/>\n\t<meta property=\"og:image:width\" content=\"1500\" \/>\n\t<meta property=\"og:image:height\" content=\"727\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/png\" \/>\n<meta name=\"author\" content=\"John Berrie\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@zukeneurope\" \/>\n<meta name=\"twitter:site\" content=\"@zukeneurope\" \/>\n<meta name=\"twitter:label1\" content=\"Verfasst von\" \/>\n\t<meta name=\"twitter:data1\" content=\"John Berrie\" \/>\n\t<meta name=\"twitter:label2\" content=\"Gesch\u00e4tzte Lesezeit\" \/>\n\t<meta name=\"twitter:data2\" content=\"2 Minuten\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\/\/www.zuken.com\/en\/blog\/defining-and-routing-pcb-constraints-for-ddr3-memory-circuits-how-to-movies\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/www.zuken.com\/de\/blog\/defining-and-routing-pcb-constraints-for-ddr3-memory-circuits-how-to-movies\/\"},\"author\":{\"name\":\"John Berrie\",\"@id\":\"https:\/\/www.zuken.com\/de\/#\/schema\/person\/8d518971503143c61c140e354e3f3266\"},\"headline\":\"Defining and Routing PCB Constraints for DDR3 Memory Circuits: How-to Movies\",\"datePublished\":\"2013-08-20T09:37:32+00:00\",\"dateModified\":\"2023-05-12T13:55:56+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\/\/www.zuken.com\/de\/blog\/defining-and-routing-pcb-constraints-for-ddr3-memory-circuits-how-to-movies\/\"},\"wordCount\":354,\"image\":{\"@id\":\"https:\/\/www.zuken.com\/en\/blog\/defining-and-routing-pcb-constraints-for-ddr3-memory-circuits-how-to-movies\/#primaryimage\"},\"thumbnailUrl\":\"https:\/\/www.zuken.com\/de\/wp-content\/uploads\/sites\/8\/2019\/04\/pcb-constraints-featured-img.png\",\"keywords\":[\"Constraint Management\",\"Electronic\",\"High-speed PCB Design\",\"How to\",\"Routing\"],\"articleSection\":[\"PCB Design\"],\"inLanguage\":\"de-DE\"},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.zuken.com\/de\/blog\/defining-and-routing-pcb-constraints-for-ddr3-memory-circuits-how-to-movies\/\",\"url\":\"https:\/\/www.zuken.com\/en\/blog\/defining-and-routing-pcb-constraints-for-ddr3-memory-circuits-how-to-movies\/\",\"name\":\"Defining and Routing PCB Constraints for DDR3 Memory Circuits - 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