DS-CR maintains electronics design data in a vault with controlled access and revision control. That data must be distributed outside the vault to support various business activities such as fabrication, assembly, and supply chain management.
Oftentimes when we’re working on schematics, the panel menus take up a ton of space on the screen. This is where the Design Gateway auto-hide feature comes in handy.
Simply draw a Dragon area around your BGA. Then select the Dragon area and create a strategy to fanout the pads of your BGA - Watch movie
Creating pin pairs in the Constraint Browser is fine for one or two nets at a time, but if you want to create pin pairs for a whole design, I recommend using an easy, single-step macro.
Did you know when editing lengthening patterns in CR-8000 Design Force, you can modify the lengthening pattern, and meet your constraints all in one step?
CR-8000 Design Force 2017 has improved the offset via function by adding efficiency in pulling out tracks from vias, creating BGA designs and build-up designs. The controls are based on the following...
A common task that is often dreaded among PCB designers is having to relocate a large point-count BGA that’s fanned out, and even partially escaped routed, to the opposite side of a PCB.
One of the more powerful capabilities of a good data management system such as DS-CR (formerly known as DS-2) is searching and the ability to generate reports. A great example is the ability to generate Where-used information. These types of reports are extremely useful when performing impact assessments where ...
Have you ever finished generating the manufacturing release package for the latest product design and then it occurred to you that something may be wrong? Imagine, it’s Thursday night and you just finished a nice dinner with the family. Your daughter’s soccer team won and the Broncos are playing the Chiefs tonight. It will be great to relax and enjoy the game.
DDR4, the fourth generation of DDR SDRAM technology, is the latest and greatest SDRAM standard and will continue to be until the fifth generation is released. The new standard features a point-to-point architecture that offers superior timing margins.
This is the second in my series of blog posts looking at the challenge of maintaining PCB signal integrity with now-common ultra-high speeds and growing adoption of PCB design environments to design in true 3-D. Today I focus on vias and the use of return vias to overcome the issues highlighted in Part 1.
Ultra-high signal speeds demand detailed consideration of the third dimension in PCB design, including via structures and layer stacks. Today I’m going to focus on the challenge. In my two subsequent posts I’ll be reviewing what PCB designers can do to meet that challenge.
As companies benefit from the global supply chain in terms of lower production costs and faster turnaround times, they are also exposing their intellectual property to third parties, including PCB design data.
As Zuken technology partners, we are often asked about how best to set PCB constraints for double-data-rate (DDR) memory, and how to route to those constraints. This question arose recently when we were asked to create a common style of DDR3 design for training, and we tried mining the web for detailed information on PCB constraints. There had to be something out there, we thought.
Previously I introduced you to the concept of S-Parameters, and now I’m going to explain a bit more about measuring them and simulating with S-Parameter models.
I’d like to explain to you in straightforward terms what S-Parameters are and why they’re so useful. When I say “straightforward”, I mean that in a technical sense, but this is a specialised area. If you’re not designing high-speed PCBs, or you don’t know much about signal integrity, you might want to tune out now.