What drives the features that are added or updated in a new release? The majority of the changes or additions in any Zuken tool release are customer-driven. Our customers provide valuable insight into emerging technologies, process and methodology changes, and the direction in which their EDA needs are taking them. This post focuses on the high points of the CR-8000 2020 release.
CR-8000 2020 is Zuken’s flagship PCB design platform, and I’m pleased to share some of the most exciting details of the new product release with you. But before we get into the new product release discussion, you may be wondering why we call it a platform and not a tool. CR-8000 2020 has all the bells and whistles for electronic subsystem development.
In today’s global value chains, data exchange and re-reuse are vital to support collaboration and productivity. But most data formats are proprietary. For any organization with an extensive database of ECAD data, the need for data migration will eventually arise.
The benefits of developing all boards of a system concurrently on a single CAD canvas. Stacking PCBs, as opposed to connecting with cables, in multi-board design is a current and highly popular trend, as manufacturing costs are reduced and reliability improved.
With every software release, you’ll find hundreds of enhancements, and CR-8000 Design Force 2019 is not an exception. Some are flashy and exciting, while others are, well, more utilitarian. But each and every one of them makes the product better. In this post, I’ll review my favorite 6 new routing enhancements in CR-8000 Design Force 2019.
To keep a good high-speed signal quality from driver to receiver on a PCB is not an easy task for designers. One of the most challenging issues is managing the propagation delay and relative time delay mismatches. Let me take you through the process...
What IC designers do to help us route high-speed PCBs
PCB designers typically have little or no experience with SPICE applications. No worries, follow along with me and get to know your SPICEs!
Every day, more and more of our lives become connected with IoT technology. With billions of smart products already out there.
In part 1 of this blog we took a back-to-basics approach and discussed line impedance and its effects in signal integrity. As every electrical conductor comprises capacitance, an inductance, and a frequency-dependent ohmic resistance, and with increasing frequencies, these electrical characteristics will influence and distort the signal.
Impedance and impedance control belong to the oldest and most often discussed topics in PCB design. They are especially important with the high-speed design when related to signal integrity. In this, the first of a two-part blog, we’ll go back to the basics of impedance/impedance control and consider what influences line impedance. In part two, we’ll set about controlling it.
PCB designers working with advanced and complex designs are constantly pushing the boundaries to satisfy the signal integrity of routed differential pairs and busses. Those who work with flexible and flex-rigid PCB designs are perhaps the most demanding of all. A while ago, the introduction of the curved corner style for routing trunks in CADSTAR made a big difference to this group of users.
Have you ever finished generating the manufacturing release package for the latest product design and then it occurred to you that something may be wrong? Imagine, it’s Thursday night and you just finished a nice dinner with the family. Your daughter’s soccer team won and the Broncos are playing the Chiefs tonight. It will be great to relax and enjoy the game.
DDR4, the fourth generation of DDR SDRAM technology, is the latest and greatest SDRAM standard and will continue to be until the fifth generation is released. The new standard features a point-to-point architecture that offers superior timing margins.
This is the second in my series of blog posts looking at the challenge of maintaining PCB signal integrity with now-common ultra-high speeds and growing adoption of PCB design environments to design in true 3-D. Today I focus on vias and the use of return vias to overcome the issues highlighted in Part 1.
Ultra-high signal speeds demand detailed consideration of the third dimension in PCB design, including via structures and layer stacks. Today I’m going to focus on the challenge. In my two subsequent posts I’ll be reviewing what PCB designers can do to meet that challenge.