FPGA and PCB Co-Design
The Graphical Pin Manager offers a straightforward FPGA and PCB co-design flow, from top level HDL description to schematic symbols, as well as to the physical I/O information for layout, thus reducing design cycle time and optimizing system performance. It automatically creates multi-instance split FPGA symbols from BSDL and pin constraints data. Pin attributes are shared through circuit, layout, and FPGA. Graphical Pin Manager interfaces directly with state-of-the-art FPGA design tools Altera Quartus II, Xilinx ISE, Actel Libero, and Lattice ispLEVER.
HDL simulation
Design Gateway supports the co-simulation of hierarchical analog and digital functional blocks and programmable devices through native HDL simulation by Active-HDL or ModelSim, as well as logic synthesis through built-in support for Synplify Pro.
