Concurrent FPGA & PCB Design

Support for Large Pin Number Devices

Component Designer provides support for large pin-count devices including CPLDs and FPGAs. It allows for editing of symbol shapes and property data and offers various import/export functions to increase data re-use efficiency. A parametric symbol generation automatically generates symbols based on property and pin data definitions (for example, in ASCII or CSV list formats) and all types of ASCII data can be exported from generated symbols. The pin-data browser enables editing from a spreadsheet-like environment and a dedicated DRC is provided for checking the data needed for symbol generation.

All types of symbol splitting are supported. If FPGA or ASIC multi-pin components are too large to be drawn in the schematic diagram, or there is a need to make symbol flow easier to understand, symbols can be freely split to make descriptions easier. Schematics can then be used directly in System Designer with two-way annotation between System Designer and Board Designer.

Symbol generation based on pin-assignment data from language design environments including VerilogVHDL, VHDL, Pin Report, VHDL Template Data, etc. is supported, in addition to the use of symbol data an pin assignment data. The following are also supported:

  • Altera (Quartus)
  • Altera ( Max+plus II)
  • Actel (Designer)
  • Xilinx (M1)
  • Lattice

Pin constraint files can be output as synthesis constraint conditions to logical synthesis tools such as Synplify from Synplicity. 

 

HDL Designer

High level language descriptions in VHDL or Verilog-HDL can easily be generated from the schematic in a visual environment using HDL Designer. In addition to performing netlist creation, HDL Designer automatically generates both HDL templates for input waveforms and test bench data including connection definitions. Input test waveforms are held in multiple files that are easily selectable. Control files for a range of simulators are created automatically. Recommended language design environments include the Active-HDL simulator (which enables integration with FPGA vendor tools), ModelSim, Polaris, and Synplify/Synplify Pro.