Physical Design
CR-5000 is comprised of intuitive layout tools fully integrated with system design and analysis tools, as well as layout verification tools, enabling an interactive work flow between schematic entry and board layout. The powerful placement and routing tools of CR-5000 are optimized for speed and accuracy, tackling today’s dense PCB design challenges with creativity and intelligent automation.
Constraints Management
The CR-5000 Constraint Manager provides a fully integrated, constraints-driven design methodology to meet high-speed performance or explosion protection requirements, reducing design costs and time-to-market by eliminating unnecessary prototypes and re-engineering cycles. It provides an easy-to-use spread-sheet-like GUI with cross-probing to schematics and layout.
Parallel Layout & Analysis
CR-5000 Lightning provides a fully integrated, complete signal integrity, power integrity, and EMC verification toolset. What-if analyses for changes to the layer stack, different track widths or track-to-track spacing, can be easily performed for optimizing single-ended or differential impedance, and crosstalk effects.
Concurrent FPGA & PCB Design
CR-5000 provides a fast and efficient solution for I/O synchronization between FPGA devices and the PCB board, enabling top-down concurrent design of FPGAs and the PCB, reducing the design cycle time and optimizing system performance. CR-5000 interfaces directly with state-of-the-art FPGA design tools from Altera, Xilinx, or Lattice.
Design Re-use
Layout, Placement & Routing
CR-5000 Board Designer facilitates the intelligent and smooth development of schematics into layout, allowing the designer to quickly and easily create, re-use or adapt designs. Everyday tasks are made intuitive and automated for complex placement patterns, speeding up the most challenging implementations. Advanced interactive placement and routing tools are available – as well as fast automatic concurrent placement and an automatic router, capable of simultaneous routing of multiple nets.