CADSTAR FPGA version 11

With the introduction of CADSTAR 11,  the CADSTAR FPGA module has received various updates regarding the ease of use and support of libraries.

  • New libraries
  • New flow charts
  • Improved Scripts
  • Improved condition coverage
  • Enhanced symbol generation wizard to output multiple gates (improvement for high pin-count devices such as FPGA’s)
  • Output Multi Gate Data File from symbol generation wizard
  • Import FPGA/Multi Gate data wizard in CADSTAR Library Editor to:
  •  Import of Multi Gate Symbols
    • Import of Pin Labels
    • Import of Pin Terminals & Automatic Assigning Pin Terminals to Physical Pins
    • Footprint Import of Pin Swap rules

Besides the already existing:

  • support of Actel, Altera, Lattice, Quicklogic an Xilinx flows from one universal project manager that controls all the design files for simulation, synthesis, place and route and pin assignment to the PCB.
  • Pin synchronization is often far from optimal for PCB routing; this new integrated solution supports the  I/O synchronization between the FPGA device and the PCB board. CADSTAR FPGA supports  forward- and back-annotate pin assignment changes in order to optimize PCB routing.
  • Create the FPGA component  with CADSTAR's PCB component BGA wizard or the Schematic Symbol Block wizard
  • One integrated design flow for FPGA and PCB design
  • No more manual creation of matching description of the FPGA to use in the PCB design or physical design
  • Easy adoption of FPGA in the product design
  • Maintain competitive flexibility late into the design cycle
  • Forward- and back-annotate pin assignment changes and pin swaps

As usual we have an evalutation version of this software ready for you to test, which you can download here!