IPC Silicon Valley Chapter Luncheon Meeting
Milpitas, CA, USA
408.943.9080
Milpitas, CA, USA
Date: August 13, 2008
Time: 11:30am to 1:30pm
Location:
The Beverly Heritage Hotel
1820 Barber Lane
Milpitas, CA 95035
Tel: 408.943.9080
Zuken Applications Engineer, Griff Derryberry, will be presenting as part of the luncheon.
| DDR Memory Design and Verification for PWB Designers and EEs |
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When Double Data Rate (DDR, DDR2 or DDR3) memory is introduced into a PCB design flow, older techniques lose their validity and accurate high-speed design becomes essential. A straightforward technical summary of double data rate memory and the challenges that accompany its introduction will be followed by practical examples based on real-world experience. The presenter will provide valuable insights to both Electronic Engineers and PCB Designers, for whom this presentation can forearm against unexpected, complex, and costly design iterations that often accompany the adoption or upgrading of Double Data Rate memory. |
- Further Information: Visit the IPC local chapter website
Register