What’s New in CR-8000 2014 and 2014.1

CR-8000 2014.1Zuken’s CR-8000, the industry’s only product-centric design solution, continues to lead the way with next-generation tools capable of creating today’s and tomorrow’s complex product designs. CR-8000 2014 and 2014.1 offer many enhancements to improve product delivery schedules and reduce costly, error-prone steps in the design process.

System Planner, Design Gateway, Design Force, and DFM Center – the core of Zuken’s CR-8000 2D/3D multi-board and IC packaging design solution – contain enhancements that include new placement and routing functionality for both conventional and high-speed designs, 3D mechanical enclosure clearance checking, and interfaces to third party simulation tools.

CR-8000 is the complete solution for your system-level, single and multi-board product design requirements. In addition to the features highlighted below, further information is available in the product release notes.

2014

2014.1

 

Improved drawing functionality and linkage to MCAD tools

CR-8000 System PlannerSystem Planner has improved drawing functionality in both Logical and Physical Visionaries. The Logical Visionary includes additional stencils to assist with the creation of block diagrams. Any image in the clipboard can be pasted into either logical or physical planning stages as a “comment” shape. 

Additional improvements include:

  • Properties changed in a circuit that has been exported from System Planner can be reloaded into the source System Planner data. When a Design Gateway schematic that had previously been exported from System Planner is updated, the Design Gateway updates are then automatically reflected in System Planner’s various planning stages.
  • IDF data can be imported into System Planner. For example, 3D IDF data can be imported and viewed in the physical planning stage.

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Reusable constraints and signal continuity checks

Design Gateway signal checkWhen using Design Gateway’s multi-board functionality, net properties can be checked for consistency between the various board level schematics within the overall system. Users can also probe from the connector of one board in the system to the connector(s) of other boards in the system to quickly and easily confirm connections between the various circuits.

Within Design Gateway’s hierarchical design functionality, a new check for mismatches between the block pin label and the net/bus label is available. This will greatly reduce the chance of accidental connection errors.

Constraint information for each functional block is directly associated with the block circuit, enabling copying and editing of constraints by block. Constraints can be managed at the block level and, more importantly, the constraints associated with reuse circuits are also reusable. This reduces the need to manage all constraints from the top level circuit.

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Enhanced placement and routing

Design Force pin pair reportDesign Force has added placement and routing templates to enable designers who work with bus routing or flex circuits to follow either reference routing or the board outline, then save the route as a template for parallel routes within the same design. When placing components support for a new “unplaced” status has been added providing greater flexability when moving and placing parts. For high-speed designs, topology templates can be created based on reference designs that include guidelines for track lengths, widths and spacing – greatly reducing the effort to configure and manage constraints, especially with differential pair routing. When routing a differential pair, Design Force not only displays the length of the entire track, it also displays the length from each source pin along with the length difference. The Pin Pair Route Report supports the highlighting of pin-pairs on the canvas from the Constraint Browser. Support for bent differential/bundle routes allows for faster interactive routing without the need to digitize precise positions for each corner.

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Signal Integrity, Power Integrity and EMI Analysis enhancements

Design Force analysis resultsCR-8000 simulation and analysis tools support eye pattern analysis, enabling the verification of results using an eye pattern diagram. During waveform analysis of DDR clock or fast differential signals, verification can be carried out using colored eye patterns and superimposed bits. Support for parameter sweep analysis of transmission lines and passive component constants has also been added. This provides increased operational efficiency in reusing sweep condition settings and ease in verifying sweep results for multiple conditions. Users can check cross-sections of transmission lines in the electrical viewer/editor, taking into account the etch factor. This makes verification more intuitive and considers trapezoidal cross sections.

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3D mechanical enclosure clearance verification

Design Force 3D clearance checkMulti-board product design – a unique feature of CR-8000 permitting the coordinated design of multiple boards in one product – enables checking of 3D clearance between boards directly within the PCB design environment. It also reports and cross-probes to any clearance violations between objects including board outlines, components, nets and mechanical data.

 

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Interface with third party simulation tools

Design Force third party analysisDesign Force 2014 has increased support for a number of third party simulation and analysis tools. Users may:

  • Import conductor figures generated in AWR Microwave Office into Design Force using the new Import IFF function.
  • Import data on the optimization of decoupling capacitors from ANSYS PI Advisor into Design Force using the new Import PI Advisor function.
  • Exchange bidirectional information with Agilent ADS using the new ADS Board Link file format. 
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New CR-8000 Component Editor compatible with CR-5000 Component Manager (2014.1)

CR-8000 Component EditorCR-8000 offers a new Component Editor that is fully compatible with the existing CR-5000 Component Manager. The user interface for footprint editing is similar to Design Force and DFM Elements, with features that include a tabbed ribbon and dockable/undockable layer and property panels. Support for multiple windows allows for the view and edit of more than one footprint in the same session. Pin information is visible and editable in a table format that supports copy and pasting to Excel for easy creation of a pin table.

 

 

 

 

 

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Chip-package-board improvements (2014.1)

Design Force chip package boardThe Design Force chip-package-board improvements include:

  • Import of GDS data is supported to allow for the efficient creation of a chip footprint within Design Force.
  • Package design functionality has been improved with the ability to import and export net assignment information using a csv file.
  • Swap nets will swap the pin objects associated with a trace, greatly improving the ability to manage bundles of nets and their connected objects.
  • Nets between routes can be automatically assigned after the fan-in and fan-out operations typically associated with co-design or advanced packaging operations are completed.
  • Spacer components can be generated as pin-less components

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ADM improvements to support Board Designer to Design Force transition (2014.1)

Design Force ADMDesign Force no longer runs ADM using the DFM Center check engine, but instead uses the same check engine as Board Designer. As a result the ADM rule manager, the check engine, and the check results are now the same between Board Designer and Design Force. ADM can be executed with a frame select (similar to DRCs), or ADM can be executed in batch mode from the CR-8000 desktop. Execution from the CR-8000 desktop provides an alternative to starting Design Force in order to run manufacturing audits.  

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