Design Force for IC, Package and PCB Co-Design
Design Force offers the industry’s first native 3D environment supporting a true hierarchy relationship between the chip, package and PCB in a system. This helps design teams work together concurrently to perform true co-design of the system, with the flexibility to support existing methodologies and work flows. Design Force includes a multi-board Constraint Manager to easily define the connectivity between the chip, package and board, and help users to cross-probe and visualize the system-level interconnect then report the net length result.
- Multi-board constraint browser simplifies hierarchical construction of systems to view and analyze system-level interconnects
- Chip or package-centric interposer design supported with through-silicon-vias (TSV), and bidirectional support with IC layout tools using LEF/DEF
- Support for OpenAccess allows the design of chip redistribution layers and interposers with native IC-level design and manufacturing rules
- Conduct ball-map optimization with co-design of packages and PCBs
- Conduct quick feasibility routing studies of chip RDL and packages to reduce layer count and improve design performance between the chip, package and board
Design Force works natively in an OpenAccess environment and can bi-directionally exchange LEF/DEF files with IC layout tools. This allows co-design with chip-level design and manufacturing rules. Users can optimize I/O pin assignment bump and ball patterns, RDL and interposer routing, and die escape routing to improve signal performance, routability of signals across the system, and reduce layer cost at the chip, package and board level.
During the exploration phase, Design Force enables engineering teams to conduct path finding and feasibility studies earlier in the design process by creating or reusing design data to conduct what-if analysis. With this true co-design platform, designers can go from exploratory to design implementation in one common environment, and conduct signal and power integrity analysis concurrently, or interface to best-in-class simulation and analysis tools from Ansys, Keysight, National Instruments, CST and Synopsys.
Zuken is working closely with IEEE and JEITA to support new industry standards, such as the new Large Scale Integrated (LSI) LSI-Package-Board (LPB) format. LPB allows cross-discipline design teams to exchange system-level netlists, component information, design rules and more. This intelligent approach for exchanging design information within the design process helps eliminate the costly errors that occur when using non-engineering formats such as text files or spreadsheets.
IC Package Design
Steve Watt, Senior Applications Engineer and Humair Mandavia, Executive Director Zuken SOZO Center, discuss the issues driving chip-package co-design