Aldec
Leading provider of HDL design verification software and hardware-based acceleration solutions for high-density FPGAs and ASICs. Utilizing direct compile simulation and patented Incremental Prototyping, Aldec provides a high performance HDL verification tool suite as well as a complete set for design entry, HDL debugging and advanced project management tools.
Active-HDL
Active-HDL is a complete FPGA verification environment with advanced graphical design entry, performance-driven mixed HDL verification and automatic testbench tools. Active-HDL's environment gives designers the independence to invoke third party logic synthesis and place and route tools from within a completely integrated, easy-to-use design environment. Active-HDL also interfaces with all industry-leading products, providing designers the freedom to use the tools of their choice to best meet the needs of each design.
Riviera
Riviera is the ultimate mixed VHDL and Verilog ASIC design verification solution. Using a "best-in-class" approach, Riviera was designed to offer the most versatile VHDL, Verilog and mixed simulation point tool available. The environment is modular and includes an HDL editor, IEEE Compliant VHDL and Verilog simulators, Waveform Viewer and advanced debugging tools. Riviera is ideal for RTL debugging, long regressions testing and team-based design methodologies.
How they fit with Zuken products:
Aldec's Active-HDL and Riviera provide leading simulation to Zuken'sSystem Designer. Active-HDL and System Designer (for VISULA & CR-5000 users) provide the complete PCB layout/schematic capture tool for logic designers working on a PC platform. System Designer invokes Active-HDL in batch mode through Active-HDL's VSIMSA, allowing the logic designer to work uninterrupted in the System Designer environment. System Designer users can invoke the Active-HDL HDL Editor to edit the HDL modules from the generated schematic. In the HDL editor, designers can use advanced features such as a built-in language assistance, auto-complete and auto-format and cross probe error messages to ensure the integrity of the HDL code. The user can then simulate the code with Active-HDL's verification tool, which then displays waveform results so that users can graphically view the simulation results.
The integration between Riviera and System Designer provides the most advanced PCB solution on the market with performance-driven results for UNIX, Linux and Windows platforms. System Designer interfaces with Riviera through the HDL Designer. Riviera enables the designer to edit modules in System Designer file through its advanced editing options such as syntax highlighting, collapsible text sections and customizable preferences. The editor is integrated with the compiler and the simulator to simplify debugging and enable breakpoint setting and quick location of compilation errors. Once the HDL language has been completed, Riviera's simulator provides the fastest simulation on the market. Users can also generate a waveform file to graphically view their simulation results and make any changes if necessary.
The integration between Active-HDL, Riviera and System Designer allows PCB designers to access the most advanced tools without leaving their PCB design environment. Integration and high-performance simulation ensure that the PCB design will run with efficiency and integrity.