PCB Analysis and Verification
Many of today's digital designs incorporate devices and technologies that require complex strategies to maintain signal integrity and reliability, where high-speed interfaces such as DDR and PCI Express impose specific timing demands that can no longer be resolved using traditional methods.
CADSTAR Signal Integrity
CADSTAR Signal Integrity Verify offers a complete pre- and post-layout signal integrity toolset that enables the engineer to organize, constraint, explore and analyze the design to minimize risk, reduce the number of prototypes and shorten development cycles.
Seamlessly integrated into the CADSTAR Design suite, CADSTAR Signal Integrity Verify utilizes the Constraint Manager spreadsheet-style interface that also simplifies design navigation and constraint entry for the CADSTAR Place and Route high-speed router, Signal Integrity Verify and Power Integrity Advance tools.
The graphical Scenario Editor lets you explore alternate design strategies to assess the best approach to meet your design objectives. You can model a virtual prototype using vendor-supplied IBIS models or generic devices from the built-in library, to evaluate different termination styles and net topologies.
CADSTAR Signal Integrity Verify works in both time- and frequency-domain modes to analyze transmission line parameters, provide fast analysis of reflection and crosstalk, and measure timing and delay characteristics. Interactive or batch mode options return a range of results including impedance, coupled line, S-parameter, fast Fourier transformation and eye diagrams, while automatic signal evaluation provides a full range of numeric data points.
Experiment with passive device values or transmission line length using Parameter Sweep to determine optimal values. Passive SPICE models can also be used and equivalent circuit models can be created to model passive parasitic devices.
Power Integrity Advance
CADSTAR Power Integrity Advance provides fast and practical power integrity and electromagnetic interference analysis within the CADSTAR PCB design flow, offering EMI, AC and DC power analysis to help you determine the best decoupling and power distribution strategy for your layout.
Designs that utilize numerous complex high pin-count ICs such as FPGAs, DSPs and CPUs operate on multiple voltage rails, requiring careful planning of the power distribution system to minimize parasitic noise and fast switching currents that can negatively impact system performance and EMC behavior.
Power Integrity Advance provides full board EMC screening for both differential and common mode board level EMC, allowing the Layout Specialist to identify potential electromagnetic emission hotspots at an early stage and resolve them by revising component placement, routing, layer assignment and power distribution strategies.
DC Analysis creates an equivalent DC circuit of your PCB that includes model information to verify DC voltage drop and current flow, helping to identify design features such as plane splits or areas of high via density that may cause voltage drop at the target device.
AC Analysis verifies plane impedance characteristics to assist the design engineer in the planning and selection of the decoupling capacitor network, helping to optimize board real estate and determine the correct distribution of decoupling capacitor values.
EMC Adviser checks are driven by a set of in-built EMC rules which check your design for different aspects of EMC, using results from the Field Solver to produce transmission line parameters. The tool analyses the design and produces ratings which indicate the probability of problems occurring in the design. The problematic design items are automatically highlighted in different colors depending on the severity of the problem.