Via Count Information

A 'Max Pin Pair Vias' constraint has been added along with a matching result.

The constraint can be set for Net Classes, Buses, Differential Pairs, Skew Groups and Electrical Nets. Also a delay constraint can be set on an electrical net, this applies to the delay between each driver-receiver pair on the electrical net, unless a specific constraint has been set between a pin pair. If it has, that constraint is applied instead.

Constraint hierarchy

The following figure shows the hierarchy for the new 'Max Pin Pair Vias' constraint;

Note, the most constraining value from any higher level applies, not the value set at the lowest level.

Max pin pair vias on a pin pair

This constrains the maximum number of vias between the two pins in the pin pair. It can be set on pin pairs consisting of any combination of component pins.

Max pin pair vias on an electrical net

When this constraint is set on an electrical net, it constrains the maximum number of vias on any pin pair within the electrical net.

Max pin pair vias on a differential pair

When this constraint is set on an differential pair, it constrains the maximum number of vias on any pin pair within either electrical net in the differential pair.

Max pin pair vias on a bus

When this constraint is set on a bus, it constrains the maximum number of vias on any pin pair in any item (electrcial net or differential pair) within the bus.

Max pin pair vias on a skew group

When this constraint is set on a skew group, it constrains the maximum number of vias on any pin pair in the skew group.

Max pin pair vias on an electrical net class

When this constraint is set on an electrical net class, it constrains the maximum number of vias on any pin pair in any electrical net in the net class.

Max pin pair vias report

Selecting the 'Max Pin Pair Vias' report from the 'Utilities' menu will produce a report similar to the below for the selected design items. This lists the maximum via constraint for each selected pin pair, as well as the number of vias in the design;