What's New in CADSTAR 11 FPGA 8.2 (for Active-HDL 8.2)

The following is a brief overview of new features and changes introduced to Active-HDL 8.2 (BUILD 1986, 07/24/2009)

Licensing

• Active-HDL 8.2 may require validation of your existing maintenance contract. The latest version requires a valid maintenance contract as of 07/01/2009.

Compiler and Simulator

NOTE: Due to internal changes in the compiler and simulator as well as updates in third-party tool libraries, all user-defined libraries should be re-compiled after the installation of Active-HDL 8.2. The installation program of version 8.2 delivers and installs only the updated system and vendor-specific libraries that do not require re-compilation after Active-HDL is installed.
All existing designs will not have any problems associated with re-compiling the libraries. If you update Active-HDL to version 8.2 and do not re-compile your design libraries, the following error message will be displayed in the Console window:

# ELBREAD: Warning: Files created by the old version of the compiler found.
# ELBREAD: Error: Library '<library_name>' has incompatible format. Recompile all library units.

General

• The approach to controlling read and write access to design objects during simulation has changed. In the previous version of Active-HDL, the compiler running in the -O3 mode could block access to signals that did not affect simulation results (i.e. to signals that neither drove other signals nor were recorded to a file). This was indicated by a message printed in the Console window:

Warning: DAGGEN_0525: Read access to some signals in unit <unit_name> was blocked. Signals marked as unreadable cannot be accessed with macro commands, graphical tools, or VHPI applications. Compile with -O2, -O1, or -O0 to disable this optimization.

Starting from version 8.2, the compiler no longer blocks read access to any signal in any mode (-O3, -O2, -O1, -O0). Instead, access can be controlled at the simulation initialization stage with the +access +r, +access +w, and +access +r+w options of the asim command. The asim command (contrary to the compiler) has access to the complete design so it can perform more design optimizations. Except for shorter simulation runtimes, this may also imply generating warnings similar to the warning shown below, e.g. when adding signals to the Waveform Viewer or the simulation database:

Warning: "XYZ" does not have read access. Use switch +access +r for this region.

To enable access, pass the +access +r argument to the asim command or specify access settings in the Simulation | Access to Design Objects category in the Design Settings dialog box. Note that in many scenarios, access to a complete design is not required. Therefore, +access +r, +access +w options can be followed by either a hierarchical path specification (+p+<path>+...) or a unit specification (+m+<unitname>+...) identifying design regions and/or design units where read or write access is required. The simulator may disable access in all other locations thus improving simulation performance.
The new solution is consistent with Verilog where read and write access is also specified at the simulation initialization stage using the same command line options. It is also more flexible (changing access requirements does not require recompilation of source files). Note, however, that in some cases the compiler running in the -O3 mode may disable read access to selected signals due to other optimizations.

• The new Performance Optimization category has been added to the Preferences dialog box. This category provides options that allow optimizing design performance at the cost of debugging capabilities and visibility of design objects during simulation. The settings specified in this category are inherited while creating a new design and they determine selected compilation and simulation options available in the Compilation and Simulation categories of the Design Settings dialog box.

• The Post Simulation Debug Mode can be turned on when the Accelerated Waveform is selected as the default waveform viewer. In order to run simulation in this mode, you need to initialize it with the Initialize Post Simulation Debug command of the Simulation main menu and choose a *.vcd file or a simulation database (*.asdb) with a history of traced objects saved in the previous simulation session. The *.psd files are still supported but initializing the debugging session in the off-line mode requires the use of the Standard Waveform Viewer.

VHDL Compilation and Simulation

• Compilation of VHDL files containing many library units has been accelerated. Selected vendor libraries, e.g. the unisim library from Xilinx compile up to two times faster.

• VHDL simulations run 5% faster on the average with selected designs running up to 60% faster.

• The simulator can now accelerate VHDL models at the simulation initialization stage by blocking read and/or write access to selected signals. For selected designs this can reduce simulation runtimes by 50%.

• Significant improvements can be observed in designs that make an extensive use of the case statement. Selected designs can simulate twice as fast.

• Processes sensitive to a clock signal that change the driven signal (or signals) in each clock cycle simulate faster. The examples are processes modeling registers or counters.

• Memory allocation has been reduced by 5 to 10 percent.

• Active-HDL 8.2 provides support for the most recent version of the VHDL standard - IEEE Std 1076™-2008. The -2006 compiler option was replaced with the new -2008 argument. The GUI settings in the Preferences, Design Settings, and File Properties dialog boxes have also been updated accordingly.

The following new language features are supported in this version of Active-HDL:

For additional information about the new VHDL constructs supported in this release, refer to the Compilation | VHDL Compilation | VHDL 2008 section in the on-line documentation.

NOTE: The -2006 compiler argument (and corresponding GUI setting) will not be supported in the next version of Active-HDL and the new -2008 argument will be used instead.

The following changes and improvements to VHDL simulation are also available:

• The -g and -G arguments for asim (i.e. the arguments that assign generic values) can now be used to assign values whose type is an array of arrays (e.g. an array of elements of the std_logic_vector type). The array value should be enclosed in parenthesis; the array elements should be quoted and separated by a comma. Assuming that the type of the generic is defined as follows:

subtype myarr_t is bit_vector (3 downto 0);
type mygeneric_t is array (2 downto 0) of myarr_t;

the value of ("0000","0010","0111") could be assigned to the mygeneric generic by using the following command line:

asim -gmygeneric=("0000","0010","0111") top

(SPT19928)

• Two new procedures were added to the aldec_tools package from the aldec library. This package contains the asdb_dump procedure that allows specifying signals to be recorded in the simulation database. Signal recording starts immediately after asdb_dump is executed. In the previous version of Active-HDL, it could not be stopped from VHDL code. Starting from version 8.2, the asdb_dump package contains two new procedures: asdb_dump_off and asdb_dump_on. The asdb_dump_off procedure disables recording to the database. The asdb_dump_on procedure resumes recording.

• Physical types now use a 64-bit representation. Accordingly, the following type definition is now valid.

type distance is range 0 to 2**31 * 2**31
units
mm;
cm    = 10 mm;
m     = 100 cm;
km    = 1000 m;
megam = 1000 km;
gigam = 1000 megam;
lightyear = 9460528 gigam;
end units distance;

Note that the literals used to specify the type range and secondary units must still be valid integer literals, i.e. they must fit into 32 bits. (The simulator uses a 32-bit representation for the integer type). If the literal is greater than integer'high (i.e. greater than 2**31 - 1) but equal or less than 2**32, the compiler will generate a warning but the value will be interpreted correctly.
The same limitation applies to expressions that yield values of a physical type - the integer literals used in the expression must be within the valid 32-bit range. Note that you can also use real literals instead of integers.

• The message displayed by the simulator when it fails to allocate memory requested in a user code with the VHDL allocator is now more informative. It includes both the hierarchical name of the design unit where the allocator was used and the location (the file name and the line number) of the allocation statement. (SPT20230)

Verilog Compilation and Simulation

• Active-HDL 8.2 introduces significant changes in default GUI settings for Verilog compilation and simulation. Now, the acceleration of simulation in Verilog designs (SLP engine) is enabled by default. SLP acceleration reduces the run time needed to simulate Verilog at the cost of limited visibility into the design regions during simulation. (Step simulation and code breakpoints are not available, read and/or write access to signals in the design may be disabled, collecting coverage data is disabled, etc.) To disable SLP acceleration, clear the Verilog Optimization option in the Simulation | Verilog category in the Design Settings dialog box.
  Simulations started in the command line with the use of the asim command will use SLP acceleration unless it is explicitly disabled with the -O2 argument. Previously, the SLP technology had to be enabled with the -O5 argument. Note that you do not have to disable SLP, e.g. if you only want to record signal waveforms and you do not need code debugging.
  Additionally, in order to achieve maximum performance, the default compiler settings for optimization levels and generation of debugging information have been changed for newly created designs. (No changes are introduced to predefined settings of existing user-defined designs.) Since version 8.2, the default compiler setting for the optimization level (required for e.g. Advanced Dataflow, stepping through HDL statements, setting code breakpoints, and collecting coverage data, etc.) is set to level 2 and the generation of debugging information has been disabled (the Enable Debug option in the Compilation | Verilog and Compilation | VHDL categories of the Design Settings dialog box is cleared).

• Verilog simulations that record VCD files run up to three times faster in the default -O5 mode (i.e. with the SLP acceleration enabled) and up to 50% faster in the -O2 mode (i.e. without the SLP acceleration).

• Simulations using PLI applications extensively run up to 40% faster.

• RTL simulations without SLP acceleration are 5% faster on the average and allocate less memory.

• Simulations recording VCD files may run faster. Speedups depend heavily on designs and types of recorded signals. In some benchmarked designs, simulations run up to 30% faster.

• Two new tasks are available to control recording of simulation database directly from Verilog code: $asdbDumpOn and $asdbDumpOff. These two tasks complement the functionality provided by the $asdbDump task. The $asdbDump task specifies signals to be recorded in the database. Recording starts immediately after the task is executed. Starting from version 8.2, you can stop recording with $asdbDumpOff and resume it with $asdbDumpOn.

• Automatically generated names for generate blocks now meet requirements of the IEEE Std. 1364™-2005. All unnamed generate blocks are given the name genblk<n> where <n> is the number assigned to its enclosing generate construct. The numbering of the generate constructs starts at 1 at the construct that appears textually first in a given scope. In the previous version, the names started with a number followed by the generateblock string.

SystemVerilog Compilation and Simulation

• Dynamic arrays are supported. The dynamic arrays can be used to manage collections of variables whose number changes during simulation runtime. The example below shows how to declare, create, resize, and delete such an array.

integer arr[]; //declare
initial begin
  arr = new [10]; //create
  $display( arr.size() );
  arr = new[20](arr); //resize
  $display( arr.size() );
  arr.delete(); //delete
  $display( arr.size() );
end

The array size reported by the $display task will be 10, 20, and 0.

• Associative arrays are supported. An associative array can be indexed by an arbitrary data type. Storage for new elements is allocated dynamically when the array is written to. The example below shows a declaration of a dynamic array indexed by the string type and a few assignments to the array in the initial block.

integer opcode_cnts[ string ];
initial begin
  opcode_cnts[ "ADD" ] = 3;
  opcode_cnts[ "SUB" ] = 4;
  opcode_cnts[ "JNE" ] = 4;
end

Supported associative array methods include: num (returns the number of elements), delete (removes an element form the array), exists (checks if the document exists), first, last (assign the index of the first/last element and return 1 on success), prev, and next (assign the index of the previous/next element and return 1 one on success). (SPT18135, SPT21757)

• Queues are supported. A queue is an array that grows or shrinks automatically as the number of elements changes. Elements in the queue are uniquely identified by an ordinal number. Element numbering starts with 0.

integer q[$]; //A queue of integers
integer r[$:15]; //A queue with a maximum size of 16

initial begin
  #10;
  q.push_back( 1 );
  q.push_back( 2 );
  q.push_front( 0 );
  q.push_front( 4 );

  for( int i = 0; i < q.size(); i++ )
    $display( q[i] );

  r = q [1:2];
  for( int i = 0; i < r.size(); i++ )
    $display( r[i] );

end

(SPT19488, SPT21734, SPT21735, SPT22556, SPT22656)

• Classes can be now parameterized with types. This allows writing generic code that can be reused extensively. For example, you could create a generic stack class and specify the type of elements stored in the stack with a parameter:

class stack #(type T = int);
  //...
endclass

The class could provide the following methods (note how type T is used to specify task arguments and function return values):

task push( T a );
  //..
endtask
function T pop( );
  //..
endfunction
function integer size( );
  //..
endfunction

The class, when instantiated, can be parameterized with an arbitrary type, for example:

typedef struct {
  int x;
  int y;
} point;
stack #( point );

• Operators !== and === can now be used with class handles as operands. (SPT22226)

• The foreach loop is now available and can be used to iterate over array elements, for example:

int arr[0:7]='{0,0,0,0,4,4,4,8};
initial
  foreach(arr [i])
    $display( arr[i] );

The foreach loop can iterate not only over regular arrays but also over associative arrays, dynamic arrays, and queues.

• An unpacked structure can now be assigned to another structure of the same type. Previously, such functionality was available only for packed structures.

• Unpacked structures and arrays can now be used as task and function arguments and module ports, and modports. (SPT19526, SPT22375)

• Blocking and nonblocking assignments to complete structures are supported. Additionally support for assignments to complete arrays has been improved, for example it is now possible to have a procedural assignment to a packed array or a continuous assignment to a packed array of nets. (SPT22572, SPT22373)

• A class property can be placed on a sensitivity list or in an event expression. In the previous release, only static class properties could be used as timing controls.

• The support of the string type has been enhanced:

• A variable of the string type can now be placed on a sensitivity list or in an event expression, for example:

string s;
always @( s )
  $display( "String s changed: %s", s );

You can also use string type methods on the sensitivity list, for example the len() method:

string s;
always @( s.len() )
  $display( "String length changed: %s", s );

• Structure fields and class properties can now be declared to be of type string. In the previous release, only static string properties were supported.

• Module ports can be declared as objects of the string type. (SPT22537)

• The following methods have been added to the string object: atoi(), atohex(), atooct(), atobin(), atoreal(), itoa(), hextoa(), octtoa(), and bintoa(). (SPT15376)

• The $fgets, $fread, $ferror, and $swrite system tasks can now handle correctly arguments of the string type.

Additionally:

• Functions can return values of the string type.

• Automatic tasks and functions can accept arguments of the string type.

• Class methods accept arguments of the string type and can return values of the string type.

• Variables of the string type can be declared in class methods.

• The following improvements are available for the constraint solver engine:

• The constraints definitions can include function calls.

• Fields of unpacked structures can be randomized.

• Static class properties can be randomized. Randomization of non-static class properties is not yet available.

• Parameters can be declared in the compilation unit scope. (SPT21078)

• Several improvement are available in virtual interfaces. Event control on virtual interface dynamic class properties is supported. Non-blocking assignments can be used inside virtual interfaces. (SPT20700, SPT21676)

• A clocking block may be specified for a modport. (SPT15871, SPT21180)

• Compiling code with declarations of pure virtual methods conforming to the IEEE 1800™-2005 syntax requires the uss of the -sv2k5 compiler argument. For example, the compiler will assume that the declaration below declares a pure virtual method only if -sv2k5 is passed.

virtual function void f;
endfunction

If the -sv2k5 argument is omitted, the compiler will analyze the declaration according to the rules outlined in the draft of the new revision of the standard, that is, it will assume that the declaration declares a non-pure virtual method with an empty implementation. (SPT22341)

• Constant functions can be declared in packages.

• An arbitrary cycle delay can be used in intra-assignments in a clocking drive. In the previous release, only ##1 was allowed.

• The clocking event can be passed to the sampled value functions ($sampled, $rose, $fell, $stable, $stable). Previously, only the one-argument version of those functions was supported.

• A four-argument version of the $past function is supported, i.e. the function accepts the expression2 and clocking_event arguments, as required by IEEE 1800™-2005. (SPT14379)

• The sampled value functions can be used in procedural code. (SPT19101)

• The fork ... join_any and fork ... join_none constructs are now supported. (SPT21675, SPT22557)

• Variables can be declared in unnamed blocks, for example in an unnamed always block or an unnamed initial block.

• SystemVerilog classes can contain unpacked properties, for example unpacked structures, arrays, or real values. In the previous version of Active-HDL, classes containing such properties could not be compiled (SPT20597).

• Structures and arrays can be used as task and function arguments.

• Class methods can be declared extern. This feature allows moving the method definition outside the body of the class declaration; this can improve the readability and maintainability of a code and is especially convenient for methods with large bodies.
  To move a method definition outside the class, precede the method prototype with the extern qualifier, for example:

class c;
  extern function void f;
endclass

Then, declare the method outside the class, qualifying its name with the class name and two colons, for example:

function void c::f;
  $display ("A method defined outside the class declaration.");
endfunction

If you fail to provide the method body, the compiler will not report an error. However, a fatal error will be reported when the simulation is initialized.
Extern class methods in Active-HDL are visible as separate library units and can be compiled independently of class declarations. This feature further enhances code management. The Compiling Code that Uses Classes in the SystemVerilog Simulation section contains tips on how to split SystemVerilog code into header files (.svh) and implementation files (.sv). The correct organization of source files can substantially reduce compilation dependencies and recompilation times, enforce proper interfaces inside the project, facilitate organizing sources into packages and libraries, and improve code reusability.

• Class handles can be cast using the $cast function and the $cast task. $cast allows you to assign a superclass handle to a subclass variable if the superclass handle refers to an object of the given subclass. This is demonstrated in the example below:

module dynamic_cast;
  class c;
  endclass

  class ce extends c;
  endclass

  c C = new;
  ce CE1 = new;
  ce CE2 = new;

  initial begin
    C = CE1; // Variable C now holds a reference
             // to a variable of class CE

  if( $cast(CE2, C) ); // so $cast succeeds.
    $display( "Cast succeeded" );

  end
endmodule

The ce class extends the c class. The CE1 object is assigned to the c variable of the C class. (It is legal to assign a subclass variable to a variable of a class higher in the inheritance tree.) Because the C variable holds a reference to a variable of the ce class, you can then cast C (superclass handle) to CE2 (subclass variable).

• A limited support for virtual interfaces is available. Virtual interfaces allow separating abstract models and test programs from the actual signals in the design. The users manipulate sets of virtual signals without having to refer to actual signals in the design. Changes to the underlying design do not necessitate changes to the code that uses virtual interfaces.
  Virtual interfaces can be used for arguments of task, function, and class methods. The example below shows the C class with a virtual interface passed to the class constructor (the new() function). Note the virtual keyword.

interface itf;
  logic req,ack;
endinterface

class C;
  virtual itf itf_var;
  function new(virtual itf itf_in);
    itf_var = itf_in;
  endfunction

  task request();
    itf_var.req = 1'b1;
  endtask

endclass

The current implementation in Active-HDL supports:

• Declarations of virtual interfaces, including declarations inside classes.

• Assignments to virtual interface variables.

• Simple read-write access to elements of a virtual interface: variables, parameters, bit selections, part selections, and concatenations; chained hierarchical references are not supported yet.

• Calling functions and tasks in the interface.

• Expressions using ==, !=, ?: operators with virtual interface operands.

• Access to virtual interface objects on sensitivity lists.

Additional information about virtual interfaces is available in the SystemVerilog Reference Guide.

• The std::randomize function supports randomization for more data types: packed structures and unions, members of both packed and unpacked structures and unions, static and non-static class properties accessed via static object references (i.e. references that are not declared inside automatic tasks and functions and created on the stack during runtime). Any nested combination of those types is also supported.

• Array literals are supported. The example below shows an array literal used for assigning value at declaration:

typedef reg [0:1][0:1] R;
R r1 = '{ '{1, 1}, '{1, 0} };

The nesting of braces in the literal must follow the number of array dimensions. Using the replication expression is allowed, for example:

R r2 = '{ '{ 2{1} }, '{1, 0} };

The literal can specify the default value, for example:

typedef int T [0:31];
T t1 = '{default : 16};

Literals can also refer to fields in the array using indexes and specify the default field value, for example:

T t2 = '{0:10, 1:10, 2:10, default : 16};

(SPT17667, SPT21780, DAM602/Case ID:15608)

• Structure literals are supported. The example below shows a definition of a structure type and a variable declaration. The assignment at declaration uses a structure literal.

typedef struct {bit x; int y; real z; } S;
S s = '{1, 2, 0.0};

In this release, structure literals cannot be prefixed with a type indication.

• User-defined bins in coverpoints are supported.

• The detect_overlap member is now available in the option structure holding instance-specific coverage options. Setting this option to 1 forces the simulator to check for overlaps between coverpoint bins. If an overlap is detected, the simulator issues a warning. For example, given the following coverpoint:

coverpoint addr {
  option.detect_overlap = 1;
  bins a = { [0:31]};
  bins b = { [0:63]};
}

the simulator will issue the following warning:

Warning: RUNTIME_0206 Detected an overlap between SystemVerilog coverage bin(s) 'a', 'b' within the interval '[0:31]'.

• The two-argument variants of the get_coverage() and get_inst_coverage() methods are now available. When the two arguments are specified, both methods assign to the first argument the number of covered bins and to the second argument the number of coverage bins defined for the given coverage item.

• The following abort properties accept_on, reject_on, sync_accept_on, and sync_reject_on are now supported. The accept_on and reject_on properties are asynchronous; the sync_accept_on and sync_reject_on properties are synchronous.

• A garbage collector is available. The garbage collector automatically detects unreferenced objects (i.e. objects that can never be accessed by the application) and frees the memory occupied by those objects.

• The cover statement can be used to monitor a sequence, for example:

sequence s1;
  @(posedge clk) { a, b};
endsequence
cover sequence( s1 );

Note that the cover statement can only be used with properties in IEEE Std. 1800™-2005.

• Property evaluations are either vacuous and nonvacuous. For more information on this feature, see Assertions | Concurrent Assertions | Vacuity Feature in the SystemVerilog Reference Guide.

• New commands dedicated to Functional Coverage are available (fcover report, fcover comment, fcover clear). See Scripts below for more information.

• Functional Coverage metrics can be collected by using the newly supported covergroup and coverpoint constructs. A covergroup specification contains a set of coverage points and a clocking event that synchronizes sampling of coverage points. In the listing below, the covg covergroup is defined inside the m module. The group has only one coverage point (clrs). The coverage points are sampled at the negative edge of the clk signal. The group is then instantiated as covvar.

typedef enum bit[1:0] {
  cyan, magenta, yellow, black
} colors_t;

module m( clk, clrs );
  input bit clk;
  input colors_t clrs;
  
  covergroup covg @(negedge clk);
    option.at_least = 2;
    coverpoint clrs;
  endgroup
  covg covvar = new;
  
  // other statements
endmodule

The coverage options such as auto_bin_max, at_least, goal, and weight are supported. The get_inst_coverage and merge_instances options are also supported.
A functional coverage report can be created by using the fcover report command. The report for the code in the listing could look as follows:

FUNCTIONAL COVERAGE:
================================================================
| Covergroup                  |  Hits   |  Goal /  | Status    |
|                             |         | At Least |           |
================================================================
| TYPE tb.U1.covg             | 75.000% | 100.000% | Uncovered |
|-----------------------------|---------|----------|-----------|
| COVERPOINT tb.U1.covg::clrs | 75.000% | 100.000% | Uncovered |
|-----------------------------|---------|----------|-----------|
| bin auto(0)                 |      6  |       1  | Covered   |
| bin auto(1)                 |      1  |       1  | Covered   |
| bin auto(2)                 |      2  |       1  | Covered   |
| bin auto(3)                 |      0  |       1  | Zero      |
================================================================
| TYPE tb.U2.covg             | 75.000% | 100.000% | Uncovered |
|-----------------------------|---------|----------|-----------|
| COVERPOINT tb.U2.covg::clrs | 75.000% | 100.000% | Uncovered |
|-----------------------------|---------|----------|-----------|
| bin auto(0)                 |      6  |       1  | Covered   |
| bin auto(1)                 |      1  |       1  | Covered   |
| bin auto(2)                 |      2  |       1  | Covered   |
| bin auto(3)                 |      0  |       1  | Zero      |
================================================================
TOTAL FUNCTIONAL COVERAGE: 75.000% COVERGROUP TYPES: 2

User-defined coverage bins and the cross construct are not yet supported.

• Virtual class methods are supported. If a method is declared virtual, then a call to the method via the parent class object will call the overridden method. This principle is demonstrated in the listing below:

class b;
virtual function void f;
  $display ("function from the base class");
endfunction
endclass
 

class d extends b;
function void f;
  $display ("function from the derived class");
endfunction
endclass
 

module m;
b B;
d D;

initial begin
  D = new;
  B = D;
  B.f();
end

endmodule

The d class extends the b class and overrides the f() method declared as virtual. A call to the f() method in the base class (i.e. B.f()) executes the f() method from the derived class (i.e. D.f()). If the f() method in the base B class were not declared virtual, then B.f() would be executed instead. (Function from the base class would be displayed.) A method declared as virtual in the base class remains virtual in all classes derived from that class, either directly or indirectly.
Note that compiler assumes reg to be the default function argument type, therefore the following declarations are not equivalent:

virtual function void f (input logic r);
endfunction

virtual function void f (logic r);
endfunction

• Methods in virtual classes can be declared as pure virtual. A pure virtual method is a method without a body. The implementation of the method may be provided in classes derived from the base class. The derived class cannot be instantiated unless it provides the implementation for the virtual method.

virtual class b;
pure virtual function void f;
endclass

class d extends b;
function void f;
  $display ("function from the derived class");
endfunction
endclass

• Constants declarations can be used inside packages.

• Packages can now export symbols imported from other packages using the export keyword, for example:

package p1;
  const integer c = 1;
endpackage

package p2;
  import p1::*;
  export p1::*;
endpackage

module m;
  import p2::*;
  reg r = c; // c is now visible
endmodule

• The substr() method is available for string objects. The substr() method returns a new string created from a range of consecutive characters in the string object. The beginning and the end of the range must be specified as arguments to the substr() method. Both arguments must be integers. Character numbering starts at 0. An example is shown in the listing below. When the code is executed, the simulator will display the ring string, which is a substring of the original my string string:

string str;
initial begin
  str = "my string";
  $display (str.substr (5, 8));
end

Note that the substr() method returns an empty string when the second argument is less than the first argument or either of the arguments is out of range (i.e. it is less than 0 or more than str.len()). (SPT18138)

• Input and inout ports can be of the bit type. In the previous version, the bit type was allowed only for module output ports. (SPT15870)

• The list of port connections in a module instantiation statement can now connect two-value output port to a four-value output port in the instantiating module, or a four-value output port to a two-value output port in the instantiating module. For example, an output port of the integer type can be connected to an output port of the int type. Previously, such connections triggered an error at the initialization of simulation about an unsupported reg to reg connection. (SPT18931, SPT18933)

• Packed structures can be used as module ports. (SPT16023)

• The %m format specifier used in the action block in an assertion displays the assertion label. (SPT19125)

Mixed-Language Compilation and Simulation

• Mixed-language simulation is faster by 11% on average and up to 75% in selected cases.

• Mapping of Verilog parameters in VHDL generic maps is now more flexible. In the previous version, when a Verilog module was encapsulated as a VHDL component, Verilog parameters without the type specification and Verilog parameters of the integer type had to be mapped to VHDL generics of the integer type. Starting from Active-HDL 8.2, such parameters can also be mapped to VHDL generics of the bit_vector and std_logic_vector type.

• The algorithm of translating Verilog values to VHDL generics changed for generics of the predefined boolean, bit, and character type, enumeration types whose values are character literals and contain value '0' and '1', and for arrays of the aforementioned types. Note that this comprises both the std_logic and std_logic_vector type.
  In the previous version, the value of the Verilog parameter was always translated to an integer and then that integer was used to select one value from the enumeration type based on its position. For example, for a VHDL generic of the std_logic type declared as:

generic( g : std_logic );

the following Verilog mapping in the module instantiation statement

#(.g(1))

resulted in assigning 'X' value to the generic. ('X' is located at position one in the definition of the std_logic type.)

Starting from Active-HDL 8.2, the following mapping is used for scalar types:

If the VHDL type contains both 'X' and 'x' literals, then the Verilog value 1'bx is translated into the literal that has the greater position number in the VHDL type definition. If neither 'X' or 'x' is included in the type definition, then X is translated to '0'. The same principle applies to the 'Z' and 'z' literals.
If the VHDL generic is of an array type then, the Verilog value is translated into VHDL bit by bit. For example, the Verilog value 8'hFE mapped onto VHDL generic of the std_logic_vector (7 downto 0) type will be translated to "11110000". If the Verilog value is a string literal, then each character in the string is treated as an 8-bit wide variable; the resulting bit value is translated to VHDL bit by bit. For example, Verilog string literal "Z" is 8'h5a, which is 8'b01011010 binary. Accordingly, the VHDL generic will be mapped to "01011010".

C/C++/SystemC Compilation and Simulation

• Simulation with SystemC is faster by 7% on average and up to 25%  in selected cases.

• The SystemC ports of the bool type can now be connected to VHDL objects of the std_logic or boolean type. In the previous version, the SystemC bool type could only be mapped to the VHDL std_logic type. The type mapping (SystemC bool as std_logic or boolean) is determined by the addsc command. The default behavior has not been changed (i.e. SystemC bool types are still mapped to VHDL std_logic type). However, if you use the new -boolasbool argument of addsc, the SystemC bool type will be mapped to the VHDL boolean type; you will be able to connect SystemC ports of the bool type to VHDL objects of the boolean type (connection to an std_logic object will trigger an error).

• The TLM library version 1.0 available in the previous version of Active-HDL has been replaced with TLM 2.0.

• The MinGW package (Minimalist GNU for Windows) was updated. The updated package includes gcc 3.4.5. In the previous versions of Active-HDL, the gcc 3.4.2 was used.

Assertion-Based Verification

• The design verification based on SystemVerilog, OVA, and PSL assertions has been enhanced. The simulator can now detect and report vacuous evaluations and extra evaluations. The following assertion:

property p;
  @(posedge clk ) a |-> c;
endproperty
assert property (p);

will succeed in two distinct cases:

• The antecedent matches and the consequent evaluates to true.

• The antecedent does not match.

Whenever the antecedent sequence does not match, the evaluation attempt is vacuous. A list of SystemVerilog sequence and property operators that can be evaluated either vacuously or non-vacuously is available in the Assertions | Concurrent Assertions | Vacuity Feature section of the SystemVerilog Reference Guide.

To enable or disable the distinction between vacuous and non-vacuous evaluations for either assert or cover statements, use the new vacuity command. The distinction between vacuous and non-vacuous evaluations is by default enabled for assertion passes and the cover statements and disabled for assertion failures.

• The simulator can now report results of multiple evaluations that started at one time point. Such evaluation threads can be spawned by sequences using operators such as the repetition operator or the cycle delay operator. Consider the following property:

property p;
  @(posedge clk) a ##[1:3] c;
endproperty

The property is asserted in the following statement:

assert property (not p);

If the assertion failed because sequence a ##1 c completed successfully, then the information that a ##2 c also completed successfully (and the additional evaluation of the assertion failed) is usually redundant. Previously, such failures were not reported by the simulator.
Starting from version 8.2, Active-HDL can report additional evaluations, both for assert and for cover statements. The information obtained from such evaluations may be useful in a variety of cases, for example, when checking the functional coverage.
To force the simulator to report additional evaluations, use the new -extra argument available both for the assertion and cover command, for example:

assertion fail -extra -enable
assertion pass -extra -enable
cover -extra -enable

Generating information about the additional (extra) evaluations may adversely affect the simulation speed. Therefore, this functionality is by default disabled and, if required, must be enabled by the user with the assertion/cover commands.

• The prev, stable, rose, and fell functions can be used with the clock expression argument.

Libraries

The following changes have been introduced to the system and vendor-specific libraries delivered with Active-HDL 8.2:

• Updated Libraries
  
  HDL Synthesis
  1. Mentor Graphics Precision RTL Synthesis 2009a.76
  2. Synplicity FPGA Synthesis C-2009.06
  
  Implementation
  1. Actel Designer 8.5 SP2
  2. Altera Quartus II 9.0 SP2
  3. Lattice ispLEVER 7.2 SP2
  4. Lattice ispLEVER Classic 1.3
  5. QuickLogic QuickWorks 2009.2.2.1
  6. Xilinx ISE 11.2

• Removed Libraries
  
  Implementation
  1. Xilinx ISE 11.2 (AIM, LOGIBLOX, PLS, SPARTAN, SPARTAN2, SPARTAN2E, SPARTANX, VIRTEX, VIRTEX2, VIRTEX2P, XABELSIM, XC3000, XC4000E, XC4000X, XC5200, OVI_UNI3000, OVI_UNI5200)

Design Flow Manager

• New Flowcharts
  
  HDL Synthesis
  1. Mentor Graphics Precision RTL 2009 Synthesis (supports Precision RTL Synthesis 2009a.76) (SPT21132)
  2. Synplicity Synplify/Synplify Pro/Synplify Premier/Premier with Design Planner C-2009.03 (supports FPGA Synthesis C-2009.03) (SPT22657)
  3. Synplicity Synplify/Synplify Pro/Synplify Premier/Premier with Design Planner C-2009.06 (supports FPGA Synthesis C-2009.06) (SPT45058)
  4. Xilinx ISE/WebPack 11.1 XST VHDL/Verilog
  
  Physical Synthesis
  1. Xilinx PlanAhead 11.1
  
  Implementation
  1. Xilinx ISE/WebPack 11.1

• Updated Flowcharts
  
  HDL Synthesis
  1. Mentor Graphics Precision RTL 2008 Synthesis (supports Precision RTL 2008a2.208 OEM edition for QuickLogic) (SPT21132)
  2. Synplicity Synplify/Synplify Pro 9.6 for Lattice (supports the 9.6L3 OEM edition for Lattice)
  
  Implementation
  1. Actel Designer 8.5 (supports Service Pack 2 for Designer 8.5)
  2. Altera Quartus II 9.0 (supports Service Pack 2 for Quartus II 9.0)
  3. Lattice ispLEVER 7.2 (supports Service Pack 2 for ispLEVER 7.2)
  4. QuickLogic QuickWorks 2009.x (supports QuickWorks 2009.1.2.1, QuickWorks 2009.2.1, and QuickWorks 2009.2.2.1)

Expression Coverage

• Expression Coverage has been supplemented with Condition Coverage. Condition Coverage is a part of the Expression Coverage engine that monitors and factorizes logical expressions used in conditional statements. When the simulation session is finished, statistics are processed and saved to a coverage database (.exd). Condition Coverage data is a subset of statistics produced by the Expression Coverage engine. Condition Coverage share the database with Expression Coverage, i.e. both coverage statistics are collected simultaneously during the same simulation session.
  Reports generated by Condition Coverage are based on data extracted from the Expression Coverage database and they include only expressions used in VHDL conditional statements such as if, while, or the conditional signal assignment statement. Condition Coverage statistics can be displayed in the Code Coverage Viewer window. For additional information, refer to the Code Coverage section below. (SPT21616)

• The Expression Coverage engine can collect statistics for atomic logical expressions used in conditional statements, such as if RESET, where RESET is a boolean value. Enabling this functionality requires compilation of source files with the new -exci argument of the compiler (acom). The argument comprises the functionality of the -exc argument and should be used instead of -exc when statistics for atomic expressions are required. (SPT22813)

Code Coverage

• The Code Coverage Viewer window allows presenting Condition Coverage statistics. The Condition Coverage statistics can be displayed in the same way as Code Coverage or Expression Coverage data. To load Condition Coverage data, a coverage data filter should be set to Condition Coverage (.exd) in the Open dialog box. Otherwise, Expression Coverage statistics will be loaded and shown instead of data for Condition Coverage. For additional information, refer to the Condition Coverage Report topic in the on-line documentation.

Scripts

The following changes have been introduced to internal macro commands:

• In previous versions of Active-HDL, macros and scripts could be executed in the DO, Tcl, and Compatibility Mode. (The Compatibility Mode is a modified Tcl mode supporting the command syntax of the ModelSim® simulator.) In order to execute a script in one of the Tcl modes (the DO mode was always on), the -tcl or -msim arguments had to be passed to the do or runscript command. Active-HDL 8.2 allows switching the command interpreter from the DO mode to either the Tcl or Compatibility Mode so that the execution of regular Tcl commands is possible directly from the Console window until the end of the Active-HDL session (the command interpreter returns to the default DO mode) or the working mode is changed manually with the new scripterconf macro command. The version of the Tcl interpreter used in this release is 8.4.19.
  Due to this change, the format of the command line (e.g. the names of the predefined variables, specification of file paths and command arguments) and interpretation of commands specified within user-defined scripts or in the Console window has been updated to meet the requirements of the Tcl language. For more information, refer to the Active-HDL on-line documentation. (SPT19639)

• The new scripterconf command has been implemented. The macro allows changing the working mode of the command interpreter (DO, Tcl, or Compatibility Mode).

• The -condition argument has been added to the excoverage report command. The new argument allows generating a Condition Coverage report instead of an Expression Coverage report. The Condition Coverage report includes only expressions used in VHDL conditional statements such as if, while, or the conditional signal assignment statement. (SPT21616)

• The coverage merge command has been enhanced with two new arguments dedicated to the Merge Branches mode. The -path argument specifies the design branches from respective databases to be merged. The alternative argument, -rpath, can be used when you need to merge coverage results for selected hierarchies coming from different design regions, e.g. if you want to add individual (partial) coverage results for selected modules to the coverage result of the entire design. When the design regions being merged differ, the hierarchy paths need to be replaced before the merge starts.
  Both the arguments are available only in the branch merging mode (-merge branches) and they must follow immediately after either the -dir or -ccl argument. Multiple specification of -dir | -ccl and -path|-rpath pairs is allowed.
  The new -rpath argument is also available in the excoverage merge command. (SPT19555, SPT21566, SPT21649)

• The vacuity command is available. The command specifies whether the simulator should distinguish vacuous and non-vacuous evaluations of the assert and cover statements.

• The new arguments -vacuous and -nonvacuous are available for the assertion fail, assertion pass, and cover commands. These arguments control counting and reporting of vacuous assertion passes, assertion failures, and cover statement matches.

• The -extra argument is available for the assertion fail, assertion pass, and cover commands. The argument is used to enable monitoring of additional (extra) evaluation threads for the assert and cover statements.

• The fcover command for generating functional coverage reports has been replaced with the fcover report command. All arguments previously supported by the fcover command are now supported by the fcover report command. Additionally, the -comment argument is available. This argument specifies that the report generated by the comment should include a separate column with comments attached by the fcover comment command.

• The fcover comment command is available. The command can be used to attach comments to a covergroup or a coverpoint and to read previously attached comments. The comments can also be included in the Functional Coverage report. (The fcover report command can be invoked with the -comment argument.) Note that it is not yet possible to attach comments directly from SystemVerilog code by setting the comment field in the type_options structure. (That field is not yet available and any reference to it will trigger an error at the initialization of simulation.)

• The fcover clear command is available. The command clears the contents of the Functional Coverage database; it is possible to clear either the entire database or data for selected instances only.

• The -lcu option is available for the Verilog compiler (alog). Using this options forces the compiler to print a list of successfully compiled units. (If the option is omitted the compiler will only print the list of top-level modules.)

• The -2008 argument replaced the -2006 option of the acom, vhdlstandard, and filevhdloptions commands.

• The -enable_bp_assert argument has been implemented in the acom and alog command. The argument allows setting regular code breakpoints at lines containing the assert or cover directives.

• The -asdbsizelimit argument has been added to the syntax of the asim command. It allows specifying the maximum size (in MB) of the ASDB simulation database file. When the limit is exceeded, a warning message is printed to the Console window and signal logging stops without interrupting simulation. If argument is not specified, the default limit for the size of the *.asdb file is 15750MB.

• The -bdepagesize argument has been added to the syntax of the code2graphics command. The new argument allows specifying the size for the generated block diagram document (*.bde).

• The -l <logfile> argument is available for the asim command. Using this argument forces the application to create a log file with the contents of the Console window, similarly to the transcript file command. Logging does not terminate until you quit the application or close the log file with the transcript file -close command. (SPT21107)

• The -O2 argument has been added to the syntax of the asim command. The new argument allows disabling SLP-accelerated simulation, which is by default enabled during the initialization of simulation since Active-HDL 8.2.

• The adir macro command has been enhanced and supplemented with new arguments. The -l argument allows printing verbose information about units residing in a library, -source returns the names of library source files and -witharch prints architectures associated with each entity when listing library contents.

• The libraryinfo macro has been added. The command prints to the Console window the information about a library status, vendor, version and its description.

• The -color argument of the wave command can be used for any object when the Accelerated Waveform Viewer is selected. Previously, the color of waveform objects could be changed only for analog overlay buses in the Accelerated Waveform Viewer window or for objects displayed in the Standard Waveform Viewer/Editor window. (SPT22109, SPT21696, SPT21425, SPT21367, SPT18543, SPT18994, SPT19383, SPT18255)

• The new opendocument and closedocument commands have been implemented. The commands are the equivalent of the open and close commands but they can be used in the Tcl and Compatibility Mode.

• The -f argument has been enabled in the filelibrary, filescriptoptions, filestatus, filetype, fileveroptions, and filevhdloptions. The new argument allows specifying the path and name of a textual file containing a list of files for which new design settings are to be applied.

• The cover unfinished command has been added. The command enables reporting of the cover statements whose evaluation has not finished prior to restarting or ending the simulation session.

• The cloc macro command has been implemented. The command allows analyzing all design/resource files and languages recognized by Active-HDL and calculates statistics for blank lines, comment lines, and lines of source code. The tool can be also started from the Tools menu by using the HDL Code Statistics option. (SPT18491, SPT20874, SPT21134)

• The psd command supports now the *.asdb and *.vcd files while initializing the Post Simulation Debug Mode.

• The -preserve argument has been introduced to the syntax of the design open, workspace open, and opendesign macro commands. The new argument preserves the original design settings and prevents from turning on performance optimization options while opening for the first time a design coming from an earlier version of Active-HDL.

• It is now possible to add array slices to the waveform; for example command
      wave arr(1)(12:2)
  creates a virtual bus consisting of 11 elements starting with arr(1)(12) down to arr(1)(2). (SPT20868)

Block Diagram Editor

• The input and output terminals inherit the names and range specification of symbol pins when connected directly. In the previous versions, the default terminals names specified in the Default Names category of the Preferences dialog box were used. (SPT20267)

• The preferences of the Block Diagram Editor have been equipped with a new option that allows controlling the order in which symbol pins are inserted while generating a new BDE symbol in a library after the compilation of HDL source code. Now, you can choose between inserting the symbol pins in the alphabetical order or in the order of their declaration in HDL source code. Previously, the symbol pins were always inserted in the alphabetical order.
  The Pin order option is available in the Block Diagram Editor | Symbols Generation category of the Preferences dialog box. This option is also used by the CODE2GRAPHICS Conversion Wizard while generating new block diagrams. (SPT20266)

State Diagram Editor

• Two new subcategories have been added to the State Diagram Editor category in the Preferences dialog box. The Default Port Settings subcategory allows specifying default properties for new ports added to any state diagram document (*.asf). In turn, the Code Generation Settings subcategory provides default settings for HDL code generation. These settings are inherited while creating a new design and they are valid for all state machines in an active design. (SPT16839)

• The New State Diagram Wizard has been enhanced with an additional page that allows specifying basic elements of new state diagrams and saving the time while repeating time-consuming graphical operations, e.g. adding and placing new states. The Wizard allows you to define a Reset state, a number of machine states, a layout (pattern) of automatic state placing and distributing on a state diagram sheet (circular, linear horizontal or vertical), automatic insertion of unconditional transitions (forward, backward, or both), design unit header, and a trap or default state. (SPT16835)

• The A3 format is now supported by the State Diagram Editor. It can be selected in the Paper Size list box in the Page Setup dialog box. (SPT17422)

HDL Editor

• The HDL Editor has been equipped with a new option that indicates with a vertical dashed line the right margin of the page. Turning on the right margin indication can be useful, e.g. when you intend to format text documents before you start printing them. The number of available columns can be customized in the HDL Editor category in the Preferences dialog box. (SPT22604)

• The Find option allows now searching for user-defined strings also in comments or source code of HDL files. Previously, the search was limited to an entire document or a selected document area. (SPT16999)

• A quick search mode is available. After selecting text and hitting Ctrl+F3, the editor will search the selection forward. To search backwards, hit Ctrl+Shift+F3. If nothing is selected, Ctrl+F3 and Ctrl+Shift+F3 will search or search backwards for the word at cursor. (SPT20009)

• The Generate Structure option in the HDL Editor now recognizes comments following each other as one group. This is especially useful for reviewing files with long, initial headers (required by many companies). (SPT13882)

Waveform Viewer

Accelerated Waveform Viewer

• A new toolbar has been added to the Accelerated Waveform Viewer window. The toolbar allows modifying graphical properties of selected waveform objects (color, height, bold). (SPT20265)

• The Display tab of the Signal Properties dialog box has been equipped with the Color option. The pull-down menu with a color palette allows selecting the desired color for the selected waveform object. The color of any waveform object can also be specified while adding new objects in the command line. Refer to Scripts for additional information. (SPT22109, SPT21696, SPT21425, SPT21367, SPT18543, SPT18994, SPT19383, SPT18255)

• The Measurement Mode has been implemented. When this mode is selected, the distance between events can be measured not only with the timing cursors but also by inserting the measurement objects into the Waveform View pane. The measurements, unlike the timing cursors, are shown above the waveform objects. It is possible to measure the distance between events on the same or different signals. Except for the time value, the new mode also allows presenting the value of the signal frequence or duty cycle and the number of events, rising and falling edges, or positive and negative pulses. (SPT19680, SPT19917, SPT20748, SPT21376)

• When signals are added to the Accelerated Waveforem Viewer window by using the Add to Waveform option, the add wave command is printed to the Console window for each added signal. When the Add to Waveform Recursively option is used, wave -rec *  is printed. The add wave/wave commands are followed by a summary with the number of traced signals. The drag&drop behavior has not changed, that is only the summary is printed (without the add wave/wave commands). (SPT20005)

• Options for copying and pasting signals are available. A signal can be copied or cut from a Wave View or a List View window. Such signals can be then pasted elsewhere in the Accelerated Waveform Viewer window or in another window as long as that window it is connected to the same database. It is also possible to copy signals from the Structure tab in the Design Browser window (and then paste them to the Accelerated Waveform Viewer window). Note that you can copy all signals from a given region by selecting that region in the upper part of the Hierarchy tab and then using the Copy option. (SPT20223)

• Option Group by Hierarchy is available in the waveform context menu. The option creates virtual groups from selected signals. All signals in the given virtual group come from the same hierarchy level. The name of the virtual group is a hierarchical path of the design region.
  You can use this option to sort all signals in the waveform; simply select all signals and choose the Group by Hierarchy option - all signals will be inserted to virtual groups based on the hierarchy. Note that the Hierarchy column for a virtual group will display the hierarchical path to the design region where its elements are located. If the elements come from different hierarchies, the column is empty. This principle applies not only to virtual groups but also to other virtual objects (virtual buses and analog overlay buses). (SPT17990)

• A new Export to Macro option is available in the Export Wizard dialog box (File | Export | Waveforms). The option generates a DO macro with an add wave command for each signal displayed in the Accelerated Waveform Viewer. The macro also contains additional commands to restore timing cursors, named rows, etc. The export procedure relies on the write format command. (SPT16850)

Standard Waveform Viewer/Editor

• A new Export to Macro option is available in the Export Wizard dialog box (File | Export | Waveforms). The option generates a DO macro with a wave command for each signal displayed in the Standard Waveform Viewer/Editor. The export procedure relies on the format wave command. (SPT16850)

• Current page is now the default option in the Print dialog box. This implies that only the current page is displayed when the contents of the Standard Waveform Viewer/Editor are displayed in the print preview mode. (SPT20270)

Active-HDL Interfaces and Wizards

The following changes and improvements have been made to the built-in Active-HDL DSP interfaces:

• Interface to Simulink®
  1. A major change in the SampleTime parameter registration for HDL Black-Box was introduced. Now, the Period setting for ports is used not only to manage transactions rate between environments, but it also defines the SampleTime value registered for a port in Simulink. This makes HDL Black-Box a true multirate block. Now, connecting blocks in multirate systems is much easier (no Rate Transfer blocks are needed). This change may require some corrections of the SampleTime parameter in blocks connected to the HDL Black-Box block. (Due to the port rate changes, conflicts with other blocks may appear if they have explicit block rate specified.) In order to avoid such problems, the Sampling Compatibility Mode is implemented. It is turned on by default by the ald_UpdateModel function for models coming from versions earlier than 8.2.
  2. The sampling period for input ports can now be specified explicitly or inherited. Additionally, the sampling period of output ports can now be inherited from the specified input port.
  3. The Macro tab has been added to the Active-HDL Co-Sim dialog box. It allows specifying and executing an Active-HDL macro before the co-simulation session initializes. Such a macro can be used, e.g. to compile an HDL design and generate M-Files before co-simulation starts. A simple MATLAB expression returning the true/false value can be used to conditionally execute the macro. To prevent the macro from execution whenever co-simulation starts, a simple function, e.g. checking whether M-Files exist can be used.
  4. The ald_do function was added. It allows executing any macro command in Active-HDL from within the MATLAB Console Window or M-File.

The following changes and improvements have been made to the import of third-party projects (File | Import):

• Import of Altera Quartus II Project
  Active-HDL 8.2 allows importing projects of Altera Quartus II ver. 9.0. The process of the import can be started when a workspace is loaded. (SPT16917, SPT17505)

The following changes and improvements have been made to the built-in third-party interfaces:

• VPI Interface
  VPI iterators now return handles to gen_scope_array, gen_scope, and objects within gen_scope's.

The following changes and improvements have been made to the CODE2GRAPHICS Conversion Wizard:

• The new BDE Page Size tab has been added to the CODE2GRAPHICS Settings dialog box. The new tab allows specifying page settings (size, orientation, title table, etc.) for the generated block diagrams. (SPT20922)

Documentation

• The new VHDL 2008 section has been added to the VHDL Reference Guide. This section describes features added in the latest edition of the standard, i.e. IEEE Std 1076™-2008. Constructs not yet supported by the simulator have been omitted. The term VHDL 2008 supersedes the term VHDL 2006 used previously to informally designate the language based on subsequent drafts of IEEE Std 1076™-2008, e.g. Draft IEEE P1076™-2006/D3.2.

• The contents of the References | Package References section (describing packages STANDARD, TEXTIO, STD_LOGIC_1164, and STD_LOGIC_ARITH) and the topic describing the ENV package have been updated and they are now available in the VHDL Reference Guide that can be found in the References | VHDL Language Reference Guide section in the main TOC or from the References | Active-HDL Reference Guides | VHDL Language Reference Guide page of the Graphical View of Contents main window.

Others

• The new HDL Code Statistics tool has been added. It allows analyzing all design/resource files and languages recognized by Active-HDL and calculates statistics for blank lines, comment lines, and lines of source code. The HDL Code Statistics option added to the Tools menu starts the tool (\bin\clocgui.exe) in the GUI mode. The HDL Code Statistics window allows selecting items to analyze and specifying analysis settings prior to processing files. The tool can be also started from the Console window by using the cloc macro command. (SPT18491, SPT20874, SPT21134)

Problems Corrected in Version 8.2

VHDL Compilation and Simulation

• The compiler crashed if the subtype range was specified with attributes, the base type of the subtype was REAL, and such a subtype was used as an entity port. (SPT21274)

• A function returning a value stored in a local variable of an array type could crash the compiler if the index range of the array was determined with a call to another function. (SPT20442)

• Under specific circumstances, a runtime error could happen when a VHDL function returned a complex data structure containing a mixture of access types, arrays, and records. (SPT20827)

• The simulator sometimes did not produce meaningful error messages when the size of interface ports did not match at the design elaboration stage or a range check failed during simulation. The issue was resolved and now correct messages are reported, for example:

ELAB2_0020 Different lengths; left: 9, right: 11

or:

RUNTIME_0047 Index 2 out of range (63 downto 32).

(SPT20960, SPT21406)

• Using an illegal prefix for the 'length attribute in a complex expression could sometimes result in a confusing error about an unsupported construct. The issue has been resolved and the compiler now correctly indicates that the prefix for the attribute is illegal. (SPT21262)

• The -nowarn compiler argument (i.e. the argument to selectively suppress compiler warnings by the message ID) did not work for some messages, for example COMP96_0119 (a warning about a null range). The issue has been corrected. (SPT16478)

• An error that appeared during simulation of selected Altera models was fixed. The error resulted in attaching the 'U' driver to elements of a bus. (SPT20768)

• An issue with range calculation was resolved. (SPT20508)

• The signal_agent procedure sometimes failed to locate signals in the design if hierarchical signal names used the slash separator (/) rather than the colon separator (:). (SPT20305)

• An unknown error reported during the simulation initialization stage was fixed. (SPT21418)

• A simulation runtime error was corrected. The error happened under specific conditions when some of the source files were compiled with and some without the debugging information. (SPT22157)

Verilog Compilation and Simulation

• An issue with incorrect evaluation of a Verilog expression was resolved. (SPT21287)

• Incremental compilation of Verilog sources (alog -incr) increased the size of library files on disk even when the compiler correctly detected that the Verilog source files did not change. (SPT20878)

• The $random task did not correctly handle arguments that were a part-selection. (SPT20988)

• The `include directive was not compiled correctly if the file name to be included was specified with a text macro defined with another macro. (SPT21016)

• An issue with SDF annotation was resolved. (SPT21060)

SystemVerilog Compilation and Simulation

• The force command used with the -freeze flag could fail to drive requested values onto SystemVerilog objects of the logic type. (SPT20372) Forcing values onto objects of an enumerated type did not work correctly on occasion. (SPT21010)

Mixed-Simulation

• An issue that resulted in a runtime error during simulation of mixed VHDL-Verilog design with SLP acceleration enabled was fixed. (SPT20594)

• A problem with instantiating VHDL entities in a SystemVerilog testbench that used interfaces and modports was resolved. (SPT20500)

PSL Simulation

• An error about an unknown identifier was reported if a PSL unit referenced a VHDL type from a package located in a resource library. (SPT20203)

Debussy/Verdi Interface

• Signals from Verilog design regions created with the generate statement were sometimes recorded incorrectly in the FSDB database. (SPT20870)

PLI Interface

• An issue with the $asdbDump task was resolved. (SPT21119)

Project Management

• Folders on the Files tab in the Design Browser window were sometimes not marked correctly with the red mark when files inside such folders did not compile cleanly. This issue is now resolved and the red mark is correctly displayed. (SPT22604)

• A double click can now be used in the General | Top-level category of the Design Settings dialog box to set the top-level unit. In the previous version of Active-HDL, the Set as Top-level option had to be selected from the pop-up menu and the double click had no effect. The top-level unit can also be set by selecting that unit and clicking the Apply button. (SPT14973, SPT18485)

Block Diagram Editor

• Previously, the values in the signal, named net, and terminal probes were displayed incorrectly when the Save full signal history option was enabled during simulation. In this release, this issue is corrected. (SPT16161, SPT22781)

Standard Waveform Viewer

• The Enable Show Event Source option (asim -ses) has been improved and now it allows checking events on vectors, arrays, records, and their elements. (SPT22164)

Documentation

• The description of the VSimSA configuration file (library.cfg) has been updated. (SPT22122)

What's New in Previous Versions?

For more information about features and changes introduced to previous releases of Active-HDL, refer to the Active-HDL release history. See On-line Documentation for details.