What's New in CADSTAR FPGA 11

What's New in Service Pack 2 for Version Active-HDL
(for CADSTAR 11 FPGA) 8.1?

The following is a brief overview of new features and changes introduced to Service Pack 2 for Active-HDL 8.1 (BUILD 1864.SP2.12, 03/16/2009

 

Licensing

  • Service Pack 2 for Active-HDL 8.1 may require validation of your existing maintenance contract. The latest version requires a valid maintenance contract as of 02/01/2009.

 

Libraries

The following changes have been introduced to the system and vendor-specific libraries dedicated to Service Pack 2 of Active-HDL 8.1:

  • New Libraries

    Implementation
    1. Altera Quartus II 9.0 (CYCLONEIIILS, HARDCOPYIII, HARDCOPYIV, OVI_CYCLONEIIILS, OVI_HARDCOPYIII, OVI_HARDCORYIV)
    2. Lattice ispLEVER 7.2 SP1 (ECP3, OVI_ECP3)
    3. QuickLogic QuickWorks 2009.1.2 (CSSP_X, CSSP_Q, CSSP_PPII_PLATFORM, OVI_CSSP_X, OVI_CSSP_Q, OVI_CSSP_PPII_PLATFORM)
    4. Xilinx ISE 10.1i SP3 (secureip; the library is not included in the default installation package but can be installed separately by using a library installation package)
     

  • Updated Libraries

    Synthesis
    1. Mentor Graphics Precision RTL Synthesis 2008a.47

    Implementation
    1. Actel Designer 8.5 SP1
     

  • Removed Libraries

    Implementation
    1. Altera Quartus II 9.0 (CYCLONELPS, OVI_CYCLONELPS)

 

Design Flow Manager

  • New Flowcharts

    HDL Synthesis
    1. Synplicity Synplify/Synplify Pro/Synplify Premier 9.6 for Actel (supports the 9.6A OEM edition for Actel) (SPT21478)
    2. Synplicity Synplify/Synplify Pro 9.6 for Lattice (supports the 9.6L1 OEM edition for Lattice)

    Implementation
    1. Actel Designer 8.5 SP1 (SPT21478)
    2. Altera Quartus II 9.0
    3. Lattice ispLEVER 7.2 SP1 (SPT21333)
    4. QuickLogic QuickWorks 2008.x (supports QuickLogic QuickWorks 2008.1.1 - 2008.3.1)
    5. QuickLogic QuickWorks 2009.x (supports QuickLogic QuickWorks 2009.1.1 and 2009.1.2)

  • Updated Flowcharts

    HDL Synthesis
    1. Mentor Graphics Precision RTL 2008 Synthesis (includes the support for Precision RTL 2008a.47)
    2. Mentor Graphics Precision RTL 2008 Synthesis (includes the support for Precision RTL 2008a2.205 OEM edition for QuickLogic)

    Implementation
    1. Lattice ispLEVER Classic (supports Lattice ispLEVER Classic 1.2 SP1)
     

  • Flowchart Improvements and Changes

    QuickLogic flowchart
    1. The QuickLogic QuickWorks 2008.1.1 flowchart has been renamed to QuickLogic QuickWorks 2008.x.

 

Condition Coverage

  • A Condition Coverage report can be generated from an Expression Coverage database (.exd). The Condition Coverage report is a subset of the Expression Coverage report and includes only expressions used in VHDL conditional statements such as if, while, or the conditional signal assignment statement. Condition Coverage is not available for Verilog. For more information on how to generate the report, see the description of the exc report command in the Scripts section below.

  • Condition Coverage can now be displayed in the Code Coverage Viewer, side by side the Code Coverage. To load Condition Coverage, locate an .exd file and set the filter type in the Open dialog box to Condition Coverage (.exd). Note that Condition Coverage and Expression Coverage use the same database file (.exd). If you do not set the filter, then Expression Coverage will be shown instead of Condition Coverage.

 

Scripts

  • Service Pack 2 introduces the support for several new macro commands dedicated to the design configuration. The commands allow setting up design settings in the GUI (change selected compilation and simulation settings in the Design Settings dialog box) and can be used only when a design is loaded. The new commands can be used in the DO, Tcl, and Compatibility modes. The following macro commands have been implemented:

  • The designverdefinemacro command allows setting or changing the Defined macros option available in the Compilation | Verilog category. (SPT21189,SPT21193)

  • The designverincludedir macro command allows specifying directories to search for files included to the project with `include compiler directives by using the Include directories option available in the Compilation | Verilog category. (SPT21188, SPT21192)

  • The designverlibrarycomp macro allows specifying Verilog libraries in the Verilog libraries option available in the Compilation | Verilog category. (SPT21190)

  • The designverlibrarysim command allows defining libraries that should be searched for unknown units instantiated in Verilog when simulation is initialized. The command sets the Verilog libraries (-PL) and Verilog libraries (-L) options available in the Simulation | Verilog category. (SPT21190)

  • The designsdffile macro command specifies the parameters necessary to annotate a simulation model with timing data by using the Files - Region, Value, and Load options available in the pane of the SDF category.

  • The designsdferrorlimit command allows defining the maximum number of errors that will not yet terminate loading timing data by the SDF loader. If the error limit is exceeded, the simulation will not be initialized. The command sets the SDF error limit option available in the SDF category.

  • The designsdfnoerrors macro changes SDF errors issued by the SDF annotator to warnings. The command controls the Change SDF errors to warnings option available in the SDF category.

  • The designsdfnowarn command allows disabling generation of warnings printed to the Console window while loading SDF files. The command sets the Disable warnings from SDF reader option available in the SDF category.

  • The designsimresolution macro command can be used to change the resolution of the simulation session in the Simulation Resolution option available in the Simulation category.

  • The bdesymbollibrary macro has been implemented. The command allows adding or removing libraries from the Symbols Toolbox window. (SPT21640)

  • The syntax of the removefile command has been supplemented with new arguments. Now, the command also allows detaching files (-D) recursively (-rec) and reporting the detailed information about processed files (-verbose). The command can be used in the DO, Tcl, and Compatibility modes. (SPT21191)

  • The amap macro command has been enhanced and supplemented with the -del argument that allows removing library mappings for a user-defined library or all local or global libraries visible in the Library Manager. (SPT21194)

  • The new exist macro command has been implemented. The command allows checking if a file exists in the specified location. The macro returns 1 if the specified file exists, otherwise, 0 is returned. The new command can be used within the if construct in the DO, Tcl, and Compatibility modes.

  • The exc report command can now be used with the new -condition argument and generate a Condition Coverage report instead of an Expression Coverage report.  

 

IP Protection

  • The vlprotect tool has been renamed and replaced by protectip.

  • The set of available cipher encryption methods supported by the protectip tool has been enhanced. Now, the protectip utility can encrypt source files with the AES256-CBC cipher.

  • VHDL and Verilog source files can now be encrypted with the AES256-CBC cipher. The encrypted files can then be compiled by the VHDL or Verilog compiler. AES256-CBC is a 256 bit cipher offering a high level of security.

 

Problems Corrected in Service Pack 2 for Version 8.1

Service Pack 2 for Active-HDL 8.1 resolves the following defects:

VHDL Compilation and Simulation

  • SPT21067, SPT21117, SPT21497, SPT21554

Verilog/SystemVerilog Compilation and Simulation

  • SPT21272

Mixed-Simulation

  • SPT21327

Block Diagram Editor

  • SPT21474

State Diagram Editor

  • SPT21587

Design Flow Manager

  • SPT21150

Expression Coverage

  • SPT21108

Scripts

  • SPT21131